For receive data, rx_axis_tdata[63:0], the port is logically
divided into lane 0 to lane 7. See the following table.
| Lane/rx_axis_tkeep | rx_axis_tdata[255:0] bits |
|---|---|
| 0 | 7:0 |
| 1 | 15:8 |
| 2 | 23:16 |
| 3 | 31:24 |
| 4 | 39:32 |
| 5 | 47:40 |
| 6 | 55:48 |
| 7 | 63:56 |
| 8 | 71:64 |
| 9 | 79:72 |
| 10 | 87:80 |
| 11 | 95:88 |
| 12 | 103:96 |
| 13 | 111:110 |
| 14 | 119:112 |
| 15 | 127:120 |
| 16 | 135:128 |
| 17 | 143:136 |
| 18 | 151:144 |
| 19 | 159:152 |
| 20 | 167:160 |
| 21 | 175:168 |
| 22 | 183:176 |
| 23 | 191:184 |
| 24 | 199:192 |
| 25 | 207:200 |
| 26 | 215:208 |
| 27 | 223:216 |
| 28 | 231:224 |
| 29 | 239:232 |
| 30 | 247:240 |
| 31 | 255:248 |