The following figure shows that the instantiation of various modules and their hierarchy for a single core configuration of l_ethernet_0 example design when the GT (serial transceiver) is inside the IP core for AMD UltraScale™ /AMD UltraScale+™ devices. Re-timing registers are used for the synchronization of data between the core and the GT. Clocking helper blocks are used to generate the required clock frequency for the core.
For the AMD Versal™ platform, the gt_quad_base (GT wizard for Versal) is part of the example design only. The 40G/50G High Speed Ethernet IP and GT (serial transceiver) IP is connected in the block design using IP integrator (block automation). Figure 1 shows the hierarchy for single core configuration for Versal adaptive SoC.
Following are the user interfaces available for different configurations:
- MAC/PCS configuration
- AXI4-Stream for data path interface
- AXI4-Lite for control and statistics interface
- PCS configuration
- MII for data path interface
- AXI4-Lite for control and statistics interface
The l_ethernet_0_pkt_gen_mon module is used to generate the data packets for sanity testing. The packet generation and checking is controlled by a Finite State Machine (FSM) module.
Descriptions of optional modules are as follows:
- l_ethernet _0_trans_debug
- This module is present in the example design when you enable the Additional GT Control and Status Ports check box from the GT Selection and Configuration Tab in the AMD Vivado™ Integrated Design Environment (IDE) or the Include GT subcore in example design option in the GT Selection and Configuration tab or the Runtime Switchable mode option in the in the Configuration Tab. This module brings out all the GT channel DRP ports, and some control and status ports of the transceiver module out of the l_ethernet core.
- Retiming Registers
- When you select the Enable Retiming
Register option from the GT Selection and Configuration Tab, it
includes a single stage pipeline register between the core and the GT to ease
timing, using the gt_txusrclk2 and gt_rxusrclk2 for TX and RX paths
respectively. However, by default two-stage registering is done for the signals
between the GT and the core.Note: For Runtime Switchable, if Auto Negotiation/Link training is selected in Vivado IDE, AN operation is performed only with the 40G data rate during switchings and LT is performed in the mission mode.
The following figure shows the instantiation of various modules and their hierarchy for the multiple core configuration of the l_ethernet_0 example design.
