Feature Summary - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English
  • Supports custom preambles
  • Programmable Inter Packet Gap (IPG)
  • Simple packet oriented 128-bit straddled packet AXI4-Stream Interface for 40 Gbps and 50 Gbps operation
  • Optional 256-bit regular AXI4-Stream Interface for 40 Gbps operation
  • Optional Clause 74 Forward Error Correction (FEC)
  • 50G FEC (Ethernet Consortium Schedule 3 specification, based on IEEE 802.3 Clause 91)
  • Optional 1588v2 PTP 1-step and 2-step timestamping
  • Optional Auto-Negotiation and Link Training
Table 1. Feature Compatibility Matrix
Variant MAC PCS 128-bit Straddle Packet 2 256-bit Pause Process-ing Auto- Negotia-tion and Link Training 4 Clause 74 FEC Clause 91 RS-FEC Soft FEC RS 4 IEEE 1588 Time Stamp
AXI4-Stream
Low Latency 40G MAC + PCS X X X X  
40G MAC + PCS X X X X X X X   X
40G PCS-only X X X   X 1
Low Latency 50G MAC + PCS X X X  
50G MAC + PCS X X X X X X X X X
50G PCS-only X X X X X X 1
Runtime switchable 40/50G MAC+PCS 3 X X X - - X X X   X
Runtime switchable 40/50G PCS-only 3 - X - - - X X X   X 1
  1. Only 2-step time stamping is supported with PCS-only configurations.
  2. AMD UltraScale™ / AMD UltraScale+™ speed grade -1 does not support 40G 128-bit AXI4-Stream interface. It is recommended to use 256 bit AXI4-Stream interface for -1 speed grade.
  3. Auto Negotiation, and Link Training are not currently supported for Transceiver type GTM.
  4. Auto Negotiation, Link Training, Control, and Status Ports are not supported for Versal devices.