GT_RESET_REG: 0000 - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English
Table 1. GT_RESET_REG: 0000
Bits Default Type Signal
0 0 RW

ctl_gt_reset_all

Note: This is a clear on write register.
1 0 RW ctl_gt_rx_reset
2 0 RW ctl_gt_tx_reset