Ports under this section are available when Enable_Time_Stamping is selected from the MAC Options tab.
| Name | Size | I/O | Description |
|---|---|---|---|
| ctl_tx_systemtimerin_* | 80 | I | System timer input for the TX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions. This input must be in the TX clock domain. |
| ctl_rx_systemtimerin_* | 80 | I | System timer input for the RX. In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds. In transparent clock mode, bit 63 is expected to be zero, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions. This input must be in the same clock domain as the lane 0 RX SerDes. |
| ctl_tx_ptp_1step_enable_* | 1 | I | When set to 1, this bit enables 1-step
operation. This port is available when Include AXI4-Lite is not selected in the Configuration tab. |
| ctl_tx_ptp_latency_adjust_* | 11 | I | This bus can be used to adjust the 1-step TX
timestamp with respect to the 2-step timestamp. The units of bits
[10:3] are nanoseconds and bits [2:0] are fractional nanoseconds. This port is available when Include AXI4-Lite is not selected in the Configuration tab. |
| ctl_tx_ptp_vlane_adjust_mode_* | 1 | I | Sets the vlan adjust mode. This port is available when Include AXI4-Lite is not selected in the Configuration tab. |
| ctl_ptp_transpclk_mode_* | 1 | I | When set to 1, this input places the
timestamping logic into transparent clock mode. In this mode, the
system timer input is interpreted as a correction value. The TX adds
the correction value to the TX timestamp according to the process
defined in IEEE 1588v2. The sign bit of the correction value is
assumed to be 0 (positive time). It is expected that the corresponding incoming PTP packet correction field has already been adjusted with the proper RX timestamp. This port is available when Include AXI4-Lite is not selected in the Configuration tab. |
| stat_tx_ptp_fifo_read_error_* | 1 | O | Transmit PTP FIFO write error. A 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error. |
| stat_tx_ptp_fifo_write_error_* | 1 | O | Transmit PTP FIFO read error. A 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error. |
| tx_ptp_1588op_in_* | 2 | I | 2’b00 – No operation: no timestamp is taken and
the frame is not modified. 2’b01 – 1-step: a timestamp should be taken and inserted into the frame. 2’b10 – 2-step: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself is not modified. 2’b11 – Reserved: act as No operation. |
| tx_ptp_tag_field_in_* | 16 | I | The use of this field is dependent on the 1588 operation. |
| tx_ptp_tstamp_valid_out_* | 1 | O | This bit indicates that a valid timestamp is being presented on the TX. |
| tx_ptp_tstamp_tag_out_* | 16 | O | Tag output corresponding to tx_ptp_tag_field_in[15:0] |
| tx_ptp_tstamp_out_* | 80 | O | Time stamp for the transmitted packet SOP
corresponding to the time at which it passed the capture plane. Used
for 2-step 1588 operation. The representation of the bits contained in this bus is the same as the timer input. |
| rx_ptp_tstamp_out_* | 80 | O | Time stamp for the received packet SOP
corresponding to the time at which it passed the capture plane. This
signal is valid starting at the same clock cycle during which the
SOP is asserted for one of the segments. The representation of the bits contained in this bus is the same as the timer input. |
| tx_ptp_upd_chksum_in_* | 1 | I | TX updated UPD checksum value. This port is available when IEEE PTP Operation Mode is selected as One Step in the MAC options tab. |
| tx_ptp_tstamp_offset_in_* | 16 | I | TX PTP timestamp offset. This port is available when IEEE PTP Operation Mode is selected as One Step in the MAC options tab. |
| tx_ptp_chksum_offset_in_* | 16 | I | TX PTP check sum offset. This port is available when IEEE PTP Operation Mode is selected as One Step in the MAC options tab. |
| tx_ptp_pcslane_out_* | 2 | O | This bus identifies which of the PCS lanes that
the SOP was detected on for the corresponding timestamp. This signal is valid starting at the same clock cycle during which the SOP is asserted for one of the segments. |
| rx_ptp_pcslane_out_* | 2 | O | This bus identifies which of the PCS lanes that
the SOP was detected on for the corresponding timestamp. This signal is valid starting at the same clock cycle during which the SOP is asserted for one of the segments. |
| rx_lane_aligner_fill_0 | 7 | O | This output indicates the fill level of the alignment buffer for PCS lane0. This information can be used by the PTP application, together with the signal rx_ptp_pcslane_out_*, to adjust for the lane skew of the arriving SOP. The units are SerDes clock cycles. |
| rx_lane_aligner_fill_1 | 7 | O | This output indicates the fill level of the alignment buffer for PCS lane1. |
| rx_lane_aligner_fill_2 | 7 | O | This output indicates the fill level of the alignment buffer for PCS lane2. |
| rx_lane_aligner_fill_3 | 7 | O | This output indicates the fill level of the alignment buffer for PCS lane3. |
| gtm_txusrclk2_* | 1 | I | TX clock input to the core. Note: This port is
available when Include GT subcore in example design option is
selected from GT Selection and Configuration tab and GT Type is
GTM.
|
| gtm_rxusrclk2_* | 1 | I | RX clock input to the core. Note: This port is
available when Include GT subcore in example design option is
selected from GT Selection and Configuration tab and GT Type is
GTM.
|
| gtm_txprgdivresetdone_* | 1 | I | For more information, see Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315). |
| gtm_rxprgdivresetdone_* | 1 | I | For more information, see Virtex UltraScale+ FPGAs GTM Transceivers Wizard LogiCORE IP Product Guide (PG315). |