If you want to include IEEE clause 91 RS-FEC soft IP (for error correction) in between 50G Ethernet IP and the GT, you must select the Include Clause 91 (RS-FEC) check box in the Configuration tab. This option is available only for 50G speed.
This feature enables the IEEE Clause 91 RS-FEC soft IP component instantiated in between the 50G core and the GT. The TX SerDes lines from the 50G core is input to the RS-FEC soft IP for forward error correction encoding. The output from the RS-FEC module is fed to the GT. Similarly, the RX SerDes lines from the GT is fed to the RS-FEC module for error correction decoding and then to the 50G core.
Refer to the 50G IEEE 802.3 Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG234) (registration required) for IEEE clause 91 Reed-Solomon Forward Error Correction for the AMD LogiCORE™ IP core and its functionality.