Latency - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID

PG211

Release Date

2023-11-01

Version

3.3 English

The following table provides the measured latency information for the low latency design of the 40G/50G IP core. This is the combined RX and TX latency for the core and does not include latency in the transceiver.

Table 1. Latency Results For Low Latency Design of the 40/50G IP Core
Core	Total Latency (ns)	TX Latency (ns)	RX Latency (ns)	User bus width (bits)	SerDes data width (bits)	Core Clock Frequency (MHz)
40G MAC_PCS	99.2	35.2	64	128	32	312.5
50G MAC+PCS	84.5	25.6	58.8	128	64	390.625
40G PCS	196.5	97.5	99	128	32	312.5
50G PCS	161.8	79.2	82	128	64	390.625
40G MAC+PCS	153	64	89	256	32	312.5
These numbers include both RX and TX fabric logic, but do not include the GT. The MAC+PCS numbers are for low latency with FIFO removed. PCS/PMA always has FIFO, due to which the latency numbers are higher.