The following table describes the control
signals.
Name | I/O | Clock Domain | Description |
---|---|---|---|
ctl_rx_pause_enable[8:0] | I | rx_serdes_clk | RX pause enable signal. This input is used to
enable the processing of the pause quanta for the corresponding
priority. Note: This signal only affects the RX user
interface, not the pause processing logic.
|
ctl_tx_pause_enable[8:0] | I | clk | TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets. |