Port Descriptions - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The following tables list all ports applicable to the 40G/50G subsystem including the ports used for optional features at the name_hsec_cores hierarchy level. At the xci top level hierarchy the ports change some to include the instantiated transceiver core and other shared logic. The port list at the XCI level of the hierarchy is described in Core xci Top Level Port List in Example Design. Other Ports are described in PCS Variant and Auto-Negotiation (AN) and Link Training (LT).

The following figure shows the relationship between the hierarchical blocks and illustrates the differences among the blocks in relation to the signals.
Note: When you generate the optional AXI4-Lite registers, some of these ports can be accessed by the corresponding register instead of a broadside bus.
Figure 1. Port List Hierarchy

The following sections describe the ports. The VL_LANES parameter is 4 and the LANES parameter is 2 for 50 Gbps operation and 4 for 40 Gbps operation. For GTM, see SerDes Data Mapping for GTM.