Port List — PCS-Only - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The following table shows the 40G/50G PCS IP core ports. These are the ports when the PCS-only option is provided. There are no FCS functions and no AXI4-Stream-related ports.

The PCS does not contain the Pause and Flow Control ports. The system interface is XLGMII/50GMII instead of the AXI4-Stream.

These signals are found at the *wrapper.v hierarchy. Refer to PCS Clocking for clock domain definitions.

Table 1. PCS Variant Ports
Name I/O Clock Domain Description
Transceiver I/O
rx_serdes_data_n0 I rx_serdes_clk Serial data from the line for lane 0; negative phase of the differential signal
rx_serdes_data_p0 I rx_serdes_clk Serial data from the line for lane 0; positive phase of the differential signal
tx_serdes_data_n0 O tx_serdes_clk Serial data to the line for lane 0; negative phase of the differential signal.
tx_serdes_data_p0 O tx_serdes_clk Serial data to the line for lane 0; positive phase of the differential signal.
rx_serdes_data_n1 I rx_serdes_clk Serial data from the line for lane 1; negative phase of the differential signal
rx_serdes_data_p1 I rx_serdes_clk Serial data from the line for lane 1; positive phase of the differential signal
tx_serdes_data_n1 O tx_serdes_clk Serial data to the line for lane 1; negative phase of the differential signal.
tx_serdes_data_p1 O tx_serdes_clk Serial data to the line for lane 1; positive phase of the differential signal.
GT_reset (ctl_gt_reset_all) I async Active-High reset for the transceiver startup FSM. This signal also initiates the reset sequence for the entire IP core.
refclk_n0 I   Differential reference clock input for the SerDes, negative phase.
refclk_p0 I   Differential reference clock input for the SerDes, negative phase.
XLGMII/50GMII Interface Signals
rx_mii_d[127:0] O rx_mii_clk Receive XLGMII/50GMII Data bus.
rx_mii_c[15:0] O rx_mii_clk Receive XLGMII/50GMII Control bus.
rx_mii_clk I   Receive XLGMII/50GMII Clock input.
tx_mii_d[127:0] I tx_mii_clk Transmit XLGMII/50GMII Data bus.
tx_mii_c[15:0] I tx_mii_clk XLGMII/50GMII Control bus.
tx_mii_clk I tx_mii_clk Transmit XLGMII/50GMII Clock input.
rx_mii_reset I   Reset input for the RX XLGMII/50GMII interface.
tx_mii_reset I   Reset input for the TX XLGMII/50GMII interface.
rx_serdes_clk I   Input clock signal used for clocking the core logic of the RX PCS.
tx_core_clk I   Input clock signal used for clocking the core logic of the TX PCS.
rx_reset I rx_serdes_clk

Reset associated with the rx_serdes_clk logic.

Must be synchronous to rx_serdes_clk.

tx_reset I tx_core_clk Reset associated with the tx_core_clk logic. Must be synchronous to tx_core_clk.
XLGMII/50GMII Interface – Control/Status Signals
ctl_rx_vl_length_minus1[15:0] I static

Number of words in between PCS Lane markers minus one for RX. Default value, as defined in the IEEE 802.3, should be set to 16,383.

This input should only be changed while the corresponding reset input is asserted.

Note: When RS-FEC is enabled in the 50G core configuration, this value is set to 20479.
ctl_tx_vl_length_minus1[15:0] I static

Number of words in between PCS Lane markers minus one for TX. Default value, as defined in the IEEE 802.3, should be set to 16,383.

This input should only be changed while the corresponding reset input is asserted.

Note: When RS-FEC is enabled in the 50G core configuration, this value is set to 20479.
ctl_rx_vl_marker_id0[63:0] I static

PCS Lane marker for RX PCS lane0. For IEEE

802.3 default values, see RX and TX PCS Lane Marker Values. This input should only be changed while the corresponding reset input is asserted.

ctl_rx_vl_marker_id1[63:0] I static PCS Lane marker for RX PCS lane1.
ctl_rx_vl_marker_id2[63:0] I static PCS Lane marker for RX PCS lane2.
ctl_rx_vl_marker_id3[63:0] I static PCS Lane marker for RX PCS lane3.
ctl_tx_vl_marker_id0[63:0] I static

PCS Lane marker for TX PCS lane0. For IEEE

802.3 default values, see RX and TX PCS Lane Marker Values. This input should only be changed while the corresponding reset input is asserted.

ctl_tx_vl_marker_id1[63:0] I static PCS Lane marker for TX PCS lane1.
ctl_tx_vl_marker_id2[63:0] I static PCS Lane marker for TX PCS lane2.
ctl_tx_vl_marker_id3[63:0] I static PCS Lane marker for TX PCS lane3.
ctl_rx_test_pattern I rx_serdes_clk Test pattern enable for the RX core to receive scrambled idle pattern. Takes third precedence.
ctl_tx_test_pattern I tx_core_clk Scrambled idle Test pattern generation enable for the TX core. A value of 1 enables test mode. Takes third precedence.
stat_rx_fifo_error O rx_serdes_clk

Receive clock compensation FIFO error indicator. A value of 1 indicates the clock compensation FIFO under or overflowed. This condition only occurs if the PPM difference between the recovered clock and the local reference clock is greater than ±200 ppm.

If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation.

stat_rx_local_fault O rx_serdes_clk

A value of 1 indicates the receive decoder state machine is in the RX_INIT state.

This output is level sensitive.

stat_rx_hi_ber O rx_serdes_clk

High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by the IEEE 802.3.

Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_block_lock[3:0] O rx_serdes_clk

Block lock status for each PCS lane. A value of 1 indicates the corresponding lane has achieved a block lock as defined in Clause 82.

Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_error[7:0] O rx_serdes_clk

Test pattern mismatch increment. A

non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core.

This output is only active when ctl_rx_test_pattern is set to a 1.

This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 82.3.

This output is pulsed for one clock cycle.

stat_rx_error_valid O rx_serdes_clk Increment valid indicator. If this signal is a 1 in any clock cycle, the value of stat_rx_error is valid.
stat_rx_bad_code[1:0] O rx_serdes_clk

Increment for 64B/66B code violations. This signal indicates the number of 64b/ 66b words received with an invalid block or if a wrong 64b/66b block sequence was detected.

This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.

stat_rx_bad_code_valid O rx_serdes_clk Increment valid indicator. If this signal is a 1 in any clock cycle, the value of stat_rx_bad_code is valid.
stat_rx_framing_err_0[3:0] O rx_serdes_clk Increment value for number of sync header errors detected for PCS lane 0. The value of this bus is only valid in the same cycle that stat_rx_framing_err_valid_0 is a 1.
stat_rx_framing_err_1[3:0] O rx_serdes_clk Increment value for number of sync header errors detected for PCS lane 1.
stat_rx_framing_err_2[3:0] O rx_serdes_clk Increment value for number of sync header errors detected for PCS lane 2.
stat_rx_framing_err_3[3:0] O rx_serdes_clk Increment value for number of sync header errors detected for PCS lane 3.
stat_rx_valid_0 O rx_serdes_clk Increment valid indicator for PCS lane 0. If this signal is a 1 in any clock cycle, the value of stat_rx_framing_err_0 is valid.
stat_rx_valid_1 O rx_serdes_clk Increment valid indicator for PCS lane 1.
stat_rx_valid_2 O rx_serdes_clk Increment valid indicator for PCS lane 2.
stat_rx_valid_3 O rx_serdes_clk Increment valid indicator for PCS lane 3.
stat_rx_aligned O rx_serdes_clk

All PCS Lanes Aligned/Deskewed. This signal indicates whether or not all PCS lanes are aligned and deskewed. A value of 1 indicates all PCS lanes are aligned and deskewed.

When this signal is a 1, the RX path is aligned and can receive packet data.

When this signal is 0, a local fault condition exists.

Also corresponds to MDIO register bit

3.50.12 as defined in Clause 82.3. This output is level sensitive.

stat_rx_aligned_err O rx_serdes_clk

Loss of Lane Alignment/Deskew. This signal indicates an error occurred during PCS lane alignment or virtual lane alignment was lost. A value of 1 indicates an error occurred.

This output is level sensitive.

stat_rx_misaligned O rx_serdes_clk

Alignment Error. This signal indicates that the lane aligner did not receive the expected PCS lane marker across all lanes. This signal is not asserted until the PCS lane marker has been received at least once across all lanes.

This output is pulsed for one clock cycle to indicate an error condition.

stat_rx_status O rx_serdes_clk

PCS status. A value of 1 indicates the PCS is aligned and not in hi_ber state.

Corresponds to MDIO register bit 3.32.12 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_vl_demuxed[3:0] O rx_serdes_clk

PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-muxed that PCS lane.

This output is level sensitive.

stat_tx_local_fault O tx_core_clk

A value of 1 indicates the transmit encoder state machine is in the TX_INIT state.

This output is level sensitive.

stat_tx_fifo_error O tx_core_clk

Transmit clock compensation FIFO error indicator. A value of 1 indicates the clock compensation FIFO under or overflowed. This condition only occurs if the PPM difference between the transmitter clock and the local reference clock is greater than ±200 ppm.

If this output is sampled as a 1 in any clock cycle, the corresponding port must be reset to resume proper operation.

stat_rx_vl_number_0[1:0] O rx_serdes_clk

The value of this bus indicates which physical lane appears on PCS lane 0.

This bus is only valid when the corresponding bit of stat_rx_synced[PCS_LANES-1:0] is a 1.

These outputs are level sensitive.

stat_rx_vl_number_1[1:0] O rx_serdes_clk The value of this bus indicates which physical lane appears on PCS lane 1.
stat_rx_vl_number_2[1:0] O rx_serdes_clk The value of this bus indicates which physical lane appears on PCS lane 2.
stat_rx_vl_number_3[1:0] O rx_serdes_clk The value of this bus indicates which physical lane appears on PCS lane 3.
stat_rx_bip_err_0 O rx_serdes_clk

BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8

signature was in error. A non-zero value is pulsed for one clock cycle.

This output is pulsed for one clock cycle to indicate an error condition.

stat_rx_bip_err_1 O rx_serdes_clk BIP8 error indicator for PCS lane 2.
stat_rx_bip_err_2 O rx_serdes_clk BIP8 error indicator for PCS lane 2.
stat_rx_bip_err_3 O rx_serdes_clk BIP8 error indicator for PCS lane 3.
stat_rx_synced[3:0] O rx_serdes_clk

Word Boundary Synchronized. These signals indicate whether a PCS lane is word boundary synchronized. A value of 1 indicates the corresponding PCS lane has achieved word boundary synchronization and it has received a PCS lane marker.

Corresponds to MDIO register bit 3.52.7:0 and 3.53.11:0 as defined in Clause 82.3.

This output is level sensitive.

stat_rx_synced_err[3:0] O rx_serdes_clk

Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective PCS lane. A value of 1 indicates the corresponding PCS lane lost word boundary synchronization due to sync header framing bits errors or that a PCS lane marker was never received.

This output is level sensitive.

stat_rx_mf_len_err[3:0] O rx_serdes_clk

Virtual Lane Marker Length Error. These signals indicate whether a PCS Lane Marker length mismatch occurred in the respective lane (that is, PCS Lane Markers were received not every ctl_rx_vl_length_minus1 words apart). A value of 1 indicates the corresponding lane is receiving PCS Lane Markers at wrong intervals.

This output is pulsed for one clock cycle to indicate the error condition.

stat_rx_mf_repeat_err[3:0] O rx_serdes_clk

PCS Lane Marker Consecutive Error. These signals indicate whether four consecutive PCS Lane Marker errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane.

This output is pulsed for one clock cycle to indicate the error condition.

stat_rx_mf_err O rx_serdes_clk

PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective lane. A value of 1 indicates an error occurred.

This output is pulsed for one clock cycle to indicate the error condition.

Miscellaneous Status/Control Signals
dclk I rx_serdes_clk Dynamic Reconfiguration Port (DRP) clock input. The required frequency is set by providing the value in the GT DRP Clock field in the AMD Vivado™ IDE GT Selection and Configuration tab. This must be a free running input clock.
gt_loopback_in[12|6:0] I async

GT loopback input signal for each transceiver. Refer to the GT user guide.

6-bit width for the 50G single core, 12-bit width for 40G single core/ 50G two cores.