Product Specification - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The 40G/50G High Speed Ethernet IP subsystem provides ease of use connecting to the High Speed Ethernet core. Based on the configuration, this subsystem creates interface ports, instantiates the 40G/50G High Speed Ethernet Subsystem and high speed serialize and deserializer (SerDes) blocks, provides the appropriate clock signals, and connects to the AXI4-Stream user-side interface.

The block diagram for the 40G/50G High Speed Ethernet Subsystem is shown in the following figure. The right-hand side is the user interface and the left-hand side is the external device interface.

Figure 1. 40G/50G High Speed Ethernet Subsystem with 128-bit Straddled AXI4-Stream
Figure 2. 40G High Speed Ethernet Subsystem with 256-bit AXI4-Stream

The PCS architecture is based on distributing (or striping) parts of a packet over several (relatively) lower speed physical interfaces by the transmitting device. The receiving device PCS layer is responsible for stripping the different parts and rebuilding the packet before handing it off to the Ethernet MAC block. The receiver PCS layer must also deskew the data from the different physical interfaces as these might encounter different delays as they are transported throughout the network. Additionally, the core handles PCS Lane swapping across all received PCS Lanes, allowing the 40G/50G High Speed Ethernet Subsystem to be used with all optical transport systems.

The PCS and Ethernet MAC layers of the core operate at the maximum line-rate of the interface, and is optimized to operate in AMD FPGAs. The PCS layer includes scrambling/descrambling and 64B/66B encoders/decoders operating at full 40G/50G line rate. The Ethernet MAC block includes a high-speed and optimized Frame Check Sequence (FCS) generation and checking module. In addition to checking the FCS integrity of the packet, the FCS module is capable of optionally inserting and deleting the FCS bytes of the packet at full 40G/50G line rate.

The Control and Status block provides several statistics counters for monitoring data traffic. Additionally, the status interface of the 40G/50G High Speed Ethernet Subsystem provides detailed information about the health of the overall interface, each individual physical interface, and every single PCS lane. The status information includes sync header alignment, PCS alignment and PCS deskew status.