The following table describes the configuration and status ports when the RS-FEC feature is included.
Name | I/O | Description | Clock Domain |
---|---|---|---|
ctl_rsfec_enable | I | Changes only take effect after the reset. A new
value is sampled on the first cycle after reset. Enable RS-FEC function. 1= Enable RS-FEC 0= Bypass RS-FEC |
rx_serdes_clk |
ctl_rx_rsfec_enable_correction | I | Changes only take effect after the reset. A new
value is sampled on the first cycle after reset. Equivalent to MDIO register 1.200.0
|
rx_serdes_clk |
ctl_rx_rsfec_enable_indication | I | Changes only take effect after the reset. A new
value is sampled on the first cycle after reset. Equivalent to MDIO register 1.200.1
|
rx_serdes_clk |
ctl_rsfec_ieee_error_indication_mode | I | Changes only take effect after the reset. A new
value is sampled on the first cycle after reset.
|
rx_serdes_clk |
stat_tx_rsfec_pcs_block_lock | O | TX PCS block lock status 0=unlocked 1=locked |
tx_clk |
stat_tx_rsfec_lane_alignment_ status | O | TX PCS frame alignment status 0=unaligned 1=aligned |
tx_clk |
stat_rx_rsfec_am_lock0 | O | RX lane 1 lock status 0= unlocked 1= locked |
rx_serdes_clk |
stat_rx_rsfec_am_lock1 | O | RX lane 1 lock status 0= unlocked 1= locked |
rx_serdes_clk |
stat_rx_rsfec_lane_alignment_ status | O | RX alignment status 0=unaligned 1=aligned | rx_serdes_clk |
stat_rx_rsfec_lane_fill_0[13:0] | O | RX lane 0 additional delay. The top seven bits [13:7] of each delay bus is the number of additional clock cycles delay being added due to deskew. The bottom seven bits [6:0] of each delay bus is the fractional clock cycle delay being added due to deskew, in units of 1/66th of a clock cycle. |
rx_serdes_clk |
stat_rx_rsfec_lane_fill_1[13:0] | O | RX lane 1 additional delay. The top seven bits [13:7] of each delay bus is the number of additional clock cycles delay being added due to deskew. The bottom seven bits [6:0] of each delay bus is the fractional clock cycle delay being added due to de-skew, in units of 1/66th of a clock cycle. |
rx_serdes_clk |
stat_rx_rsfec_lane_mapping [1:0] | O | RX lane mapping bit 0= index of FEC lane carried on PMA lane 0 bit 1= index of FEC lane carried on PMA lane 1 |
rx_serdes_clk |
stat_rx_rsfec_hi_ser | O | This output is only active when the core is in bypass indication mode. It indicates when High that the number of FEC symbol errors in a window of 8192 codewords has exceeded the threshold K (417). | rx_serdes_clk |
stat_rx_rsfec_corrected_cw_inc | O | Corrected codeword count increment. | rx_serdes_clk |
stat_rx_rsfec_uncorrected_cw_ inc | O | Uncorrected codeword count increment. | rx_serdes_clk |
stat_rx_rsfec_symbol_error_ count0_inc[2:0] | O | Symbol error count increment for lane 0. | rx_serdes_clk |
stat_rx_rsfec_symbol_error_ count1_inc[2:0] | O | Symbol error count increment for lane 1. | rx_serdes_clk |