RS-FEC Functional Description - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The 50G subsystem RS-FEC feature provides error correction capability according to 50G FEC (Ethernet Consortium Schedule 3 specification, based on IEEE 802.3 Clause 91).

The feature requires the insertion of PCS alignment markers as defined in IEEE 802.3 Table 82-3. The number of words between the PCS alignment markers is 20,480.

It is possible to bypass the RS-FEC function by means of the enable signals. This bypasses the RS-FEC function and connect the PCS directly to the transceiver, with the benefit of reduced latency. Refer to the 50G IEEE 802.3 Reed-Solomon Forward Error Correction 50G IEEE 802.3 Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG234) (registration required) for the latest latency performance data in the various bypass modes.

The following feature bypass modes are selectable.

  • FEC Bypass Correction: The decoder performs error detection without correction, (see IEEE Std 802.3 section 91.5.3.3 [Ref 1]). The latency is reduced in this mode.
  • FEC Bypass Indication: In this mode there is correction of the data but no error indication. An additional signal, rx_hi_ser, is generated in this mode to reduce the likelihood that errors in a packet are not detected. The RS decoder counts the number of symbol errors detected in consecutive non-overlapping blocks of codewords (see IEEE Std 802.3 section 91.5.3.3 [Ref 1]). The latency is reduced in this mode.
  • Decoder Bypass: The RS decoder can be bypassed by setting the IEEE Error indication Low when the correction bypass and indication are in bypass mode.