RS-FEC Support - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

This section describes the optional RS-FEC function of the 50G Ethernet subsystem. The RS-FEC option must be specified at the time of generating the subsystem from the IP catalog or ordering the IP core asynchronously.

The RS-FEC block is positioned between the PCS and PMA as illustrated in 40G/50G MAC with PCS/PMA Clocking.

With reference to the following diagram, the RS-FEC core clocks and resets are equivalent to the transceiver signals, with the transceiver resets being active-High.

Figure 1. RFC Block Position