The 40G/50G High Speed Ethernet Subsystem provides status signals to identify 64b/66b words and sequences violations and CRC32 checking failures.
All signals are synchronous with the rising-edge of clk and a detailed description of each signal follows.
stat_rx_bad_fcs
When this signal is a value of 1, it indicates that the error detection logic has identified a mismatch between the expected and received value of CRC32 in the received packet.
When a CRC32 error is detected, the received packet is marked as containing an error
and is sent with rx_errout asserted during the last transfer (the
cycle with rx_eopout asserted) unless
ctl_rx_ignore_fcs is asserted.
This signal is asserted for one clock period each time a CRC32 error is detected.
stat_rx_bad_code[1:0]
This signal indicates how many cycles the RX PCS receive state machine is in the RX_E state as defined by the IEEE Std 802.3-2015.