RX and TX PCS Lane Marker Values - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The IEEE Std 802.3 defines the PCS Lane marker values, shown in the following table. BIP fields are calculated in accordance with IEEE 802.3 Clause 82.2.8.

Table 1. 40G/50G Marker Definitions
Input Signal Name Value
ctl_rx_vl_marker_id[0][63:0]

ctl_tx_vl_marker_id[0][63:0]

64'h90_76_47_BIP3_6F_89_B8_BIP7
ctl_rx_vl_marker_id[1][63:0]

ctl_tx_vl_marker_id[1][63:0]

64'hF0_C4_E6_BIP3_0F_3B_19_BIP7
ctl_rx_vl_marker_id[2][63:0]

ctl_tx_vl_marker_id[2][63:0]

64'hC5_65_9B_BIP3_3A_9A_64_BIP7
ctl_rx_vl_marker_id[3][63:0]

ctl_tx_vl_marker_id[3][63:0]

64'hA2_79_3D_BIP3_5D_86_C2_BIP7