The receive AXI4-Stream interface is similar to the transmit side, with the RX data corresponding to the received Ethernet frame. The other signals on the RX AXI bus have a meaning analogous to the signals on the TX bus.
The following table shows the AXI4-Stream receive interface signals.
| Signal | I/O | Clock Domain | Description |
|---|---|---|---|
| rx_core_clk | I | All RX AXI signals are referenced to this clock. | |
| rx_axis_tdata[127:0] | O | rx_core_clk | AXI4-Stream Data to user logic. |
| rx_axis_tuser_tvalid | O | rx_core_clk | AXI4-Stream Data Valid. When this signal is 1, there is valid data on the RX AXI data bus. |
| rx_axis_tuser_sop0 rx_axis_tuser_sop1 | O | rx_core_clk | This signal, when asserted, indicates the start of a received Ethernet frame. |
| rx_axis_tuser_eop0 rx_axis_tuser_eop1 | O | rx_core_clk | This signal, when asserted, indicates the end of a received Ethernet frame. There are two bits—one for each segment. |
| rx_axis_tuser_err0 rx_axis_tuser_err1 | O | rx_core_clk | RX AXI error indication signal.
|
| rx_axis_tuser_mty0[2:0] rx_axis_tuser_mty1[2:0] | O | rx_core_clk |
This bus indicates how many bytes of the rx_axis_tdata bus are empty or invalid for the last transfer of the current packet. This bus is only valid during cycles when both rx_axis_tuser_ena and rx_axis_tuser_eop are 1. There are two bits—one for each segment. |
| rx_axis_tuser_ena0 rx_axis_tuser_ena1 | O | rx_core_clk | Receive AXI4-Steam Enable for each Segment. When asserted, this signal indicates that data for the associated segment is valid. |
Note: In the 128-bit Straddle Packet Interface,
the TX AXIS interface is generally synchronous with
tx_out_clk and the RX AXIS interface is synchronous with rx_clk_out.