Receive AXI4-Stream Interface – 256-bit - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English
Table 1. Receive AXI4-Stream Interface
Name I/O Clk Description
rx_axis_tdata[255:0] O rx_core_clk AXI4-Stream Data to user logic
rx_axis_tvalid O rx_core_clk AXI4-Stream Data Valid. When this signal is 1, there is valid data on the RX AXI bus.
rx_axis_tuser O rx_core_clk AXI4-Stream User Sideband interface.
  • 1 indicates a bad packet has been received.
  • 0 indicates a good packet has been received.
rx_axis_tlast O rx_core_clk AXI4-Stream signal indicating an end of packet
rx_axis_tkeep[31:0] O rx_core_clk AXI4-Stream Data Control to upper layer.
Note: In 256b Packet Interface mode, both the TX and RX AXI4-Stream interfaces are synchronous to a single input clock, and rx_core_clk is typically driven by tx_clk_out.