Name | I/O | Clk | Description |
---|---|---|---|
rx_axis_tdata[255:0] | O | rx_core_clk | AXI4-Stream Data to user logic |
rx_axis_tvalid | O | rx_core_clk | AXI4-Stream Data Valid. When this signal is 1, there is valid data on the RX AXI bus. |
rx_axis_tuser | O | rx_core_clk |
AXI4-Stream User Sideband
interface.
|
rx_axis_tlast | O | rx_core_clk | AXI4-Stream signal indicating an end of packet |
rx_axis_tkeep[31:0] | O | rx_core_clk | AXI4-Stream Data Control to upper layer. |
Note: In 256b Packet Interface mode, both the
TX and RX AXI4-Stream interfaces are synchronous
to a single input clock, and rx_core_clk is typically driven by tx_clk_out.