Ports under this section are available when the Runtime switch is selected from the Configuration tab.
Name | Size | I/O | Description |
---|---|---|---|
gt_drp_done_0 | 1 | I | Indicates the completion of the GT DRP operation. Used to reset the GT module. |
ctl_rate_mode_0 | 1 | I | This signal causes the IP core to switch between 50G operation (0) and 40G operation (1). The clock frequencies must be corrected for the mode chosen. |
txpllclksel_in_0 | 8 | I | Selects the source TX PLL clock to generate TXOUTCLK from GTWIZ IP |
rxpllclksel_in_0 | 8 | I | Selects the source RX PLL clock to generate RXOUTCLK from GTWIZ IP |
txsysclksel_in_0 | 8 | I | Selects the source TX sys clock for GT Channel |
rxsysclksel_in_0 | 8 | I | Selects the source RX sys clock for GT Channel |
rxafecfoken_0 | 4 | I | Connects to RXAFECFOKEN on transceiver channel primitives |
rxdfecfokfcnum_0 | 16 | I | Connects to RXDFECFOKFCNUM on transceiver channel primitives |
speed_0 | 1 | I | This signal indicates the speed with which the
core is working: 1’b1 = 40G and 1’b0 = 50G |
anlt_done_0 | 1 | O | Indicates the completion of Auto negotiation
and Link Training This port is available when Include AN/LT logic is selected in the Configuration tab. |
rxdata_out_0 | 512 | I | RX data bus from GT IP to MAC This port is available when Include GT subcore in example design option is selected in the GT Selection and Configuration tab. |
txdata_in_0 | 512 | O | TX data bus from MAC to GT IP This port is available when Include GT subcore in example design option is selected in the GT Selection and Configuration tab. |
axi_ctl_core_mode_switch | 1 | O | This signal can be used to switch Line rate from 40G to 50G and vice-verse when you select Include AXI4-Lite in the Configuration tab and write 1 to the 0x013C self clearing register to start the GT DRP operations. |
user_reg0 | 32 | O | User-defined signal from the AXI4 register map
user_reg0 register. This port is available when Include AXI4-Lite is selected in the Configuration tab. |