STAT_CORE_SPEED_REG: 047C - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)
Document ID
PG211
Release Date
2023-11-01
Version
3.3 English
Table 1. STAT_CORE_SPEED_REG: 047C
Bits Default Type Signal
0 GUI Configured RO stat_core_speed
1 GUI Configured RO runtime_switchable 1
  1. This register is available only for the 128-bit straddled AXI4-Stream data path interface. Bits 1:0 are defined as:
    • 00 Standalone 50G
    • 01 Standalone 40G
    • 10 Runtime Switchable 50G
    • 11 Runtime Switchable 40G