The AMD 40G/50G High Speed Ethernet Subsystem implements a 40G/50G Ethernet Media Access Controller (MAC) module with 40G/50G PCS or standalone 40G/50G PCS.
The 40G/50G High Speed Ethernet Subsystem is designed to Schedule 3 of the 25G and 50G Ethernet Consortium specification r1.6 for the 50 Gbps operation and IEEE 802.3 for 40 Gbps operation; it is hardware proven, and offers system designers with a risk-free and quick path for systems that implement 40G/50G Ethernet protocols.
This guide also describes the 40G/50G High Speed Ethernet Subsystem in detail and provides the information required to integrate the 40G/50G High Speed Ethernet Subsystem into user designs. The document assumes you are familiar with the IEEE Std 802.3-2015 protocol and FPGA design and methodology. See Product Specification for detailed information. For AMD device platform-specific information, see Support. See also the IEEE Standard for Ethernet (IEEE Std 802.3-2015).