TX debug is assisted by using several diagnostic signals.
Data must be written to the TX AXI4-Stream such that there are no overflow or underflow conditions. The AXI4-Stream bandwidth must always be greater than the Ethernet bandwidth to guarantee that data can be sent without interruption.
When writing data to the AXI4-Stream, the tx_rdyout
signal must always be observed. This signal indicates whether the fill level of the TX
buffer is within an acceptable range or not. If this signal is ever asserted, you must stop
writing to the TX AXI4-Stream until the signal is deasserted.
Because the TX AXI4-Stream has greater bandwidth than the TX Ethernet
interface, it is not unusual to see this signal being frequently asserted and this is not a
cause for concern. You must ensure that TX writes are stopped when
tx_rdyout is asserted.
The level at which tx_rdyout becomes asserted is determined by a
pre-determined threshold.
When a packet data transaction has begun in the TX direction, it must continue until
completion or there can be a buffer underflow as indicated by the tx_unfout
signal. This must not be allowed to occur; data must be written on the TX AXI4-Stream without interruption. Ethernet packets must be present on the line
from start to end with no gaps or idles. If tx_unfout is ever asserted,
debugging must stop until the condition which caused the underflow has been addressed.
tx_reset/sys_reset to recover the core from the underflow issue. tx_reset resets the TX path only and sys_reset recovers the complete system.