TX Path Control/Status Ports - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The following table describes the other status/control ports.

Table 1. TX Path Control/Status Ports
Name I/O Clock Domain Description
ctl_rate_mode I static This signal causes the IP core to switch between 50G operation (0) and 40G operation (1). The clock frequencies must be corrected for the mode chosen.
ctl_tx_enable I clk TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only idles are transmitted by the 40G/50G High Speed Ethernet Subsystem. This input should not be set to 1 until the receiver it is sending data to (that is, the receiver in the other device) is fully aligned and ready to receive data (that is, the other device is not sending a remote fault condition). Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and the 40G/50G High Speed Ethernet Subsystem stops transmitting anymore packets.
ctl_tx_send_rfi I clk Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner.
ctl_tx_send_lfi I clk Transmit Local Fault Indication (LFI) code word. Takes precedence over RFI.
ctl_tx_send_idle I clk Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) code words.
ctl_tx_fcs_ins_enable I clk Enable FCS insertion by the TX core. If this bit is set to 0, the 40G/50G High Speed Ethernet Subsystem does not add FCS to the packet. It this bit is set to 1, the 40G/50G High Speed Ethernet Subsystem calculates and adds the FCS to the packet. This input cannot be changed dynamically between packets.
ctl_tx_ignore_fcs I clk

Enable FCS error checking at the AXI4-Stream interface by the TX core. This input only has effect when ctl_tx_fcs_ins_enable is Low. If this input is Low and a packet with bad FCS is being transmitted, it is not binned as good. If this input is High, a packet with bad FCS is binned as good.

The error is flagged on the signals stat_tx_bad_fcs and stomped_fcs, and the packet is transmitted as it was received.

Note: Statistics are reported as if there was no FCS error.
ctl_tx_vl_length_minus1[15:0] I static

Number of words in between PCS Lane markers minus one. Default value, as defined in IEEE Std 802.3-2015, should be set to 16,383. This input should only be changed while the corresponding reset input is asserted.

Note: When RS-FEC is enabled in the 50G core configuration, this value is set to 20479.
ctl_tx_vl_marker_id[VL_LANES-1:0][63:0] I static These inputs set the PCS Lane markers for each PCS lane. For 802.3 default values, see the IEEE Std 802.3-2015 [ IEEE Standard for Ethernet (IEEE Std 802.3-2015)]. This input should only be changed while the corresponding reset input is asserted.
stat_tx_local_fault O clk A value of 1 indicates the transmit encoder state machine is in the TX_INIT state. This output is level sensitive.
ctl_tx_custom_preamble_enable I tx_clk

When asserted, this signal treats the first 64 bits of a packet on the rx_serdes_clk as a custom preamble instead of inserting a standard preamble.

When asserted, this signals enables the use of tx_preamblein as a custom preamble instead of inserting a standard preamble.

tx_preamblein[55:0] I tx_clk This bus represents the custom preamble when the signal ctl_tx_custom_preamble_enable is asserted. It should be asserted on the first cycle of the packet (start of packet).
stat_tx_underflow_err 1 O tx_clk TX FIFO Underflow
stat_tx_overflow_err 1 O tx_clk TX FIFO Overflow
  1. These signals are available only in the 256-bit non-segmented AXI4-Stream Variant.