The following table describes the transceiver I/O ports. Refer to the Clocking topic for clock domain information.
Name | I/O | Description |
---|---|---|
rx_serdes_data[LANES-1:0][64-1:0] | I | Data bus from the SerDes macros. There are LANES rx_serdes_data
buses; one bus for each SerDes lane and each bus has 64-bits. By definition, bit [64-1] is the first bit received by the 40G/50G High Speed Ethernet Subsystem. Bit [0] is the last bit received. A typical width is 64. |
tx_serdes_data[LANES-1:0][64-1:0] | O | Data bus to the SerDes macros. There are LANES tx_serdes_data buses; one bus for each SerDes lane and each bus has 64-bits. By definition, bit [64-1] is the first bit transmitted by the 40G/ 50G High Speed Ethernet Subsystem. Bit [0] is the last bit transmitted. A typical width is 64. |
rx_serdes_clk[LANES-1:0] | I | Recovered clock of each SerDes lane. The rx_serdes_data bus for each lane is synchronized to the positive edge of the corresponding bit of this bus. |
rx_serdes_reset[LANES-1:0] | I | Reset for each RX SerDes lane. The recovered clock for each SerDes lane has associated with it an active-High reset. This signal should be asserted whenever the associated recovered clock is not operating at the correct frequency. Generally this signal is connected to a phase-locked loop (PLL) lock signal. This is a synchronous reset. |
tx_serdes_refclk | I | Reference clock for the TX datapath. This clock must be frequency locked to the tx_serdes_clk inputs. Typically, the same reference clock that is used to drive the TX SerDes is connected to this input. |
tx_serdes_refclk_reset | I | Reset for TX Reference clock. This signal should be asserted whenever the tx_serdes_refclk input is not operating at the correct frequency. This is a synchronous reset. |