Transmit AXI4-Stream Interface - 3.3 English

The following figure shows the AXI4-Stream transmit interface signals.

The synchronous TX AXI bus interface accepts packet-oriented data. All signals are synchronous relative to the rising edge of the tx_clk_out port.

The AXI4-Stream transmit interface consists of two segments, where each is 64-bits (8 bytes) wide. This segmented approach or straddled AXI4-Stream approach as it is referred to allows for greater efficiency such that a packet can start and end in any given segment or cycle.

A normal transmit cycle is shown in the following waveform. These waveforms illustrate the transfer of a 73-byte packet over a 128-bit wide AXI4-Stream interface. There are two segments shown, numbered 0 and 1.

The following figure shows a normal transmit cycle with back-to-back continuous transfers. A 115 byte packet starts on segment 0 and ends on segment 0. This is immediately followed by an 81 byte packet that starts in the same clock cycle in segment 1, and ends on segment 1.

The signals shown in the Figure 1 and Figure 2 waveforms are described in the following subsections.

tx_clk

This is the signal tx_clk_out output of the subsystem. All TX AXI signals are referenced to this clock. The frequency of this clock is normally 390.625 MHz for 50G operation and 312.5 MHz for 40G operation.

tx_axis_tready

When asserted, this signal indicates that the TX AXI4-Stream interface is able to accept data. When tx_axi_tready goes Low, you must stop sending data immediately, or it is not accepted by the TX AXI4-Stream interface.

tx_axis_tdata[127:0]

This is the bus for the frame to be transmitted.

The following figure illustrates how the start of an Ethernet frame is mapped onto the bit positions of the TX AXI4-Stream interface when tx_axis_tuser_sop0 = 1. Note the positions of the ENA0 and ENA1 signals relative to the bits positions of the TX AXI4-Stream bus.

This mapping is for a 128-bit AXI4-Stream bus.

tx_axis_tvalid

When High, this signal indicates that there is valid data on the TX AXI bus.

tx_axis_tuser_ena0, tx_axis_tuser_ena1

These signals enable the transfer of data over the TX bus when asserted. Data transfer has to be validated with the tvalid signal in order for a transfer to take place.

There is an enable signal for each AXI segment.

tx_axis_tuser_sop0, tx_axis_tuser_sop1

These signals indicate the start of an Ethernet frame in that cycle. Only one SOP is permitted in a bus cycle. There is a separate SOP signal for each AXI segment.

tx_axis_tuser_eop0, tx_axis_tuser_eop1

These signals indicate the end of an Ethernet frame in that cycle. Only one EOP is permitted in a bus cycle. There is a separate EOP signal for each AXI segment.

tx_axis_tuser_mty0[2:0], tx_axis_tuser_mty1[2:0]

These signals indicate which bytes of the corresponding segment are not used ("empty"). If tx_mtyin has a value of 0x0, there are no empty byte lanes, or in other words, all bits of the data bus are valid.

For example, if tx_axis_tuser_mty0[2:0] = 2, the last 2 bytes of the segment do not contain data, and is ignored. The value of mty can only be non-zero during the last cycle of a packet transfer (the EOP cycle).

tx_unfout

Not shown on the waveforms in the previous TX Waveform timing diagram is the tx_unfout output indicator. When this signal is High, it indicates that there has not been a sufficient data transfer and the Ethernet interface undergoes underflow. This must not be allowed to occur. You must ensure that you transfer data whenever tx_axis_tready is High until you reach the end of the Ethernet frame.

Note: When this signal sampled as 1, you need to apply tx_reset/sys_reset to recover the core from the underflow issue. tx_reset resets the TX path only and sys_reset recovers the complete system.

tx_axis_user_err0, tx_axis_user_err1

This signal is used to indicate that a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles when tx_axis_tuser_ena and tx_axis_tuser_eop are sampled as 1. When this signal is sampled as a 1, the last data word is replaced with the 802.3 Error Code control word that guarantees the partner device receives the packet in error. If a packet is input with this signal set to a 1, the FCS checking and reporting is disabled (only for that packet).

There is one tx_axis_user_err signal per segment.