User Side AXI4-Lite Write / Read Transactions - 3.3 English

40G/50G High Speed Ethernet Subsystem v3.3 Product Guide (PG211)

Document ID
PG211
Release Date
2023-11-01
Version
3.3 English

The following figures show timing diagram waveforms for the AXI4-Lite interface.

Valid Write Transactions

Figure 1. AXI4-Lite User Side Write Transaction

Invalid Write Transactions

Figure 2. AXI4-Lite User Side Write Transaction with Invalid Write Address

Valid Read Transactions

Figure 3. AXI4-Lite User Side Read Transaction

Invalid Read Transactions

Figure 4. AXI4-Lite User Side Read Transaction with Invalid Read Address