These clocks drive logic for the XLGMII/50GMII interfaces. The required clock frequency is determined by the Media Independent Interface (MII) bus width and the data rate. For example, for a 50GMII interface (50 Gb/s) and a data bus width of 128 bits, the required clock frequency is 50e9/128 = 390.625 MHz. For 40G the formula is 40e9/128 = 312.5 MHz. This clock frequency is determined according to the IEEE Standard for Ethernet (IEEE Std 802.3-2015) specification.