UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213) - 1.3 English

Document ID: PG213
Release Date: 2022-11-16
Version: 1.3 English

Introduction
Features
IP Facts
Overview
Feature Summary
Applications
Unsupported Features
Unsupported PCI Express Base Specification 3.1 Features
Unsupported PCI Express Base Specification 4.0 Features (PCIE4C)
Licensing and Ordering
Product Specification
Standards Compliance
Resource Utilization
Minimum Device Requirements
Available Integrated Blocks for PCI Express
GT Locations
Port Descriptions
AXI4-Stream Core Interfaces
64/128/256-Bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
512-bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
Other Core Interfaces
Power Management Interface
Configuration Management Interface
Configuration Status Interface
Configuration Received Message Interface
Configuration Transmit Message Interface
Configuration Flow Control Interface
Configuration Interface
Configuration Control Interface
Configuration Interrupt Controller Interface
Legacy Interrupt Interface
MSI Interrupt Interface
MSI-X Interrupt External Interface
MSI-X Interrupt Internal Interface
Configuration Extend Interface
Clock and Reset Interface
PCI Express Interface
Configuration Space
Designing with the Core
Tandem Configuration
Supported Devices
Overview of Tandem Tool Flow
Tandem PROM
Tandem PROM UltraScale+ Example Tool Flow
Tandem PROM Summary
Tandem PCIe
Tandem PCIe UltraScale+ Example Tool Flow
Loading Stage 2 Through PCI Express
Using Tandem PCIe on Zynq MPSoC Devices
Tandem PCIe Summary
Tandem PCIe with Field Updates
Reconfigurable Stage Twos
Differences from Tandem Configuration
Design Layout
Design Structure
Tandem Configuration with Field Updates Software Flow
Details on the Sample Design
Details on the Design Scripts
Bitstream Generation
Hardware Operation Details
Debugging Tandem PCIe with Field Updates Designs
Important Considerations
Known Issue and Limitation
Using Tandem With a User Hardware Design
Method 1 – Using the Existing PCI Express Example Design
Method 2 – Migrating the PCIe Design into a New Vivado Project
Tandem Configuration RTL Design
MUXing Critical Inputs
TLP Requests
Tandem Configuration Logic
User Application Handshake
Tandem Configuration Details
I/O Behavior
Configuration Pin Behavior
Configuration Persist (Tandem PROM Only)
Avoiding the Configuration Bank
PROM Selection
Programming the Device
Bitstream Encryption
Multiboot and Fallback
Tandem PROM/PCIe Resource Restrictions
Moving the PCIe Reset Pins
Non-Project Flow
Simulating Tandem Designs
Calculating Bitstream Load Time for Tandem
Example 1
Example 2
Using Bitstream Compression
Other Bitstream Load Time Considerations
Sample Bitstream Sizes
Clocking
Resets
AXI4-Stream Interface Description
Feature Overview
Supported Clock Frequencies and Interface Widths
Data Alignment Options
Straddle Option on CQ, CC, and RQ Interfaces
Straddle Option on RC Interface
Receive Transaction Ordering
Transmit Transaction Ordering
64/128/256-Bit Completer Interface
Completer Request Interface Operation
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
I/O Write Operation
I/O Read Operation
Atomic Operations on the Completer Request Interface
Message Requests on the Completer Request Interface
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Completer Completion Interface Operation
Completer Completion Descriptor Format
Completions with Successful Completion Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
64/128/256-Bit Requester Interface
Requester Request Interface Operation
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Message Requests on the Requester Interface
Aborting a Transfer
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation
Requester Completion Descriptor Format
Transfer of Completions with No Data
Transfer of Completions with Data
Straddle Option for 256-Bit Interface
Aborting a Completion Transfer
Handling of Completion Errors
512-Bit Completer Interface
Completer Request Interface Operation (512-bits)
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
I/O Write Operation
I/O Read Operation
Atomic Operations on the Completer Request Interface
Message Requests on the Completer Request Interface
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Straddle Option on CQ Interface
Completer Completion Interface Operation (512-bits)
Completer Completion Descriptor Format
Completions with Successful Completion (SC) Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
Straddle Option on CC Interface
512-Bit Requester Interface
Requester Request Interface Operation (512-bit)
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Message Requests on the Requester Interface
Aborting a Transfer
Straddle Option on RQ Interface
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation (512-bits)
Requester Completion Descriptor Format
Transfer of Completions with No Data
Transfer of Completions with Data
Straddle Option for RC Interface
Aborting a Completion Transfer
Handling of Completion Errors
Power Management
Active State Power Management
Programmed Power Management
PPM L0 State
PPM L1 State
PPM L3 State
Generating Interrupt Requests
Legacy Interrupt Mode
MSI Mode
MSI-X Mode
MSI-X Mode with Built-in MSI-X Vector Tables
Receive Message Interface
Configuration Management Interface
Enabling Loopback Master on Root Port
Link Training: 2-Lane, 4-Lane, 8-Lane, and 16-Lane Components
Link Partner Supports Fewer Lanes
Lane Becomes Faulty
Lane Reversal
Design Flow Steps
Customizing and Generating the Core
Basic Mode Parameters
Basic Tab
Capabilities Tab
PF IDs Tab
PF BARs Tab
Legacy/MSI Cap Tab
Advanced Mode Parameters
Basic Tab
Capabilities Tab
SRIOV Config Tab
SRIOV BARs Tab
MSI-X Capabilities Tab
Advanced Options Tab
Adv. Options-1
Adv. Options-2
Adv. Options-3
GT Settings Tab
Shared Logic Tab
Add. Debug Options
Core Interface Parameters Tab
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies, Management and Placement
Banking
Transceiver Placement
I/O Standard and Placement
Soft Logic Placement
Relocating the Integrated Block Core
Simulation
PIPE Mode Simulation
Synthesis and Implementation
Example Design
Overview of the Example Design
Integrated Block Endpoint Configuration Overview
Simulation Design Overview
Implementation Design Overview
Example Design Elements
Programmed Input/Output: Endpoint Example Design
System Overview
PIO Hardware
Base Address Register Support
Changing IP Catalog Tool Default BAR Settings
TLP Data Flow
Memory and I/O Write TLP Processing
Memory and I/O Read TLP Processing
PIO File Structure
PIO Operation
PIO Read Transaction
PIO Write Transaction
Configurator: Rootport Example Design
Configurator File Structure
Generating the Core
Opening the Example Design
Simulating the Example Design
Endpoint Configuration
Synthesizing and Implementing the Example Design
Test Bench
Root Port Model Test Bench for Endpoint
Architecture
Scaled Simulation Timeouts
Test Selection
Available Tests
Verilog Test Selection
Waveform Dumping
Verilog Flow
Output Logging
Parallel Test Programs
Completer Model
Test Description
Test Program: pio_writeReadBack_test0
Expanding the Root Port Model
Root Port Model TPI Task List
Test Setup Tasks
TLP Tasks
BAR Initialization Tasks
Example PIO Design Tasks
Expectation Tasks
Endpoint Model Test Bench for Root Port
Architecture
Simulating the Design
Scaled Simulation Timeouts
Waveform Dumping
Output Logging
Upgrading
Migrating from UltraScale to UltraScale+ Devices
Upgrading in the Vivado Design Suite
Managing Receive-Buffer Space for Inbound Completions
General Considerations and Concepts
Completion Space
Maximum Request Size
Read Completion Boundary
Important Note For High Performance Applications
Methods of Managing Completion Space
LIMIT_FC Method
PACKET_FC Method
RCB_FC Method
DATA_FC Method
GT Locations
Artix UltraScale+ Devices Available GT Quads
Kintex UltraScale+ Devices Available GT Quads
Virtex UltraScale+ Devices Available GT Quads
Zynq UltraScale+ Devices Available GT Quads
Debugging
Finding Help on Xilinx.com
Documentation
Debug Guide
Answer Records
Master Answer Record for the Integrated Block for PCIe
Technical Support
Hardware Debug
Integrated Debug Options
Transceiver Control and Status Ports
PCIe DRP Ports
GT DRP Ports
Using the Xilinx Virtual Cable to Debug
Overview
Host PC XVC-Server Application
Host PC XVC-over-PCIe Driver
XVC-over-PCIe Enabled FPGA Design
XVC-over-PCIe Through PCIe Extended Configuration Space (PCIe-XVC-VSEC)
XVC-over-PCIe Through AXI (AXI-XVC)
XVC-over-PCIe Register Map
PCIe Ext Capability Header
PCIe VSEC Header (PCIe-XVC-VSEC only)
XVC Version Register (PCIe-XVC-VSEC only)
XVC Shift Length Register
XVC TMS Register
XVC TDO/TDI Data Register(s)
XVC Control Register
XVC Status Register
XVC Driver and Software
Special Considerations for Tandem or Dynamic Function eXchange Designs
Using the PCIe-XVC-VSEC Example Design
Generating a PCIe-XVC-VSEC Example Design
System Bring-Up
Compiling and Loading the Driver
Compiling and Launching the XVC-Server Application
Connecting the Vivado Design Suite to the XVC-Server Application
Run Time Considerations
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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