Add. Debug Options - 1.3 English

You can select additional debug portions for debugging purposes. The parameters are described below.

Enable In System IBERT

This debug option is used to check and see the eye diagram of the serial link at the desired link speed. For more information on In System IBERT, refer to In-System IBERT LogiCORE IP Product Guide (PG246).

Important: This option is used mainly for hardware debug purposes. Simulations are not supported when this option is used.

Steps to check the eye diagram:

1. Select a suitable AMD reference board.
2. Configure the core with the following options:
   • Select Gen3, Gen2, or Gen1 link speed at any link width.
   • Select Enable In System IBERT in the Add. Debug Options page.
3. Open the Example Design.
4. Generate a .bit file and .ltx file.
5. Open Hardware Manger (HM) and configure the device using the generated .bit and .ltx file.
6. Reboot the machine to rescane and run the enumeration process again.
7. Select the Serial I/O links tab at the bottom of the HM, and create links for the scan window.
8. Select any one of the links in Serial I/O links tab, and right-click and choose scan link option.
9. For better results, try Horizontal and Vertical increment by two instead of the default value
10. After the eye scan is selected, the eye diagram will be plotted.
    Important: Enable In System IBERT should not be used with the Falling Edge Receiver Detect option in GT Settings tab. The Enable In System IBERT option in the Add. Debug Options tab also sets the GT DRP Clock Source to External in the GT Settings tab.

Enable Descrambler for Gen3 Mode

This debug option integrates encrypted version of the descrambler module inside the PCIe core, which will be used to descrambler the PIPE data to/from PCIe integrated block in Gen3 link speed mode.

Enable JTAG Debugger

This feature provides ease of debug for the following:

LTSSM state transitions

This shows all the LTSSM state transitions that have been made starting from link up.

PHY Reset FSM transitions

This shows the PHY reset FSM (internal state machine that is used by the PCIe solution IP).

Receiver Detect

This shows all the lanes that have completed Receiver Detect Successfully

Steps are the following:

1. Open a new Vivado project, and connect to the board. You should now see hw_axi_1.
2. In the Vivado Tcl Console, type source test_rd.tcl.
3. For post-processing, double-click the following:
   • draw_ltssm.tcl (Windows) or wish draw_ltssm.tcl
   • draw_reset.tcl (Windows) or wish draw_reset.tcl
   • draw_rxdet.tcl (Windows) or wish draw_rxdet.tcl

   This displays the pictorial representation of the LTSSM state transitions.