In case of Address Align Mode, the PIO design supports four discrete target spaces, each consisting of a 2 KB block of memory represented by a separate Base Address Register (BAR). Using the default parameters, the AMD Vivado™ IP catalog produces a core configured to work with the PIO design defined in this section, consisting of:
- One 64-bit addressable Memory Space BAR
- One 32-bit Addressable Memory Space BAR
You can change the default parameters used by the PIO design; however, in some cases you might need to change the user application depending on your system. See Changing IP Catalog Tool Default BAR Settings for information about changing the default Vivado Design Suite IP parameters and the effect on the PIO design.
Each of the four 2 KB address spaces represented by the BARs corresponds to one of four 2 KB address regions in the PIO design. Each 2 KB region is implemented using a 2 KB dual-port block RAM. As transactions are received by the core, the core decodes the address and determines which of the four regions is being targeted. The core presents the TLP to the PIO design and asserts the appropriate bits of (BAR ID[2:0]), Completer Request Descriptor[114:112], as defined in the following table.
| Block RAM | TLP Transaction Type | Default BAR | BAR ID[2:0] |
|---|---|---|---|
| ep_io_mem | I/O TLP transactions | Disabled | Disabled |
| ep_mem32 | 32-bit address Memory TLP transactions | 2 | 000b |
| ep_mem64 | 64-bit address Memory TLP transactions | 0-1 | 001b |
| ep_mem_erom | 32-bit address Memory TLP transactions destined for EROM | Expansion ROM | 110b |
For Dword Align Mode, the PIO design supports one target space, consisting of
2048 Bytes of memory. The memory is implemented using SDRAM. As transaction are received
by the core, the core presents the TLP to the PIO design and asserts the bits of BAR
ID[2:0], and completer request descriptor [114:112] as 001b.