The PCI configuration space consists of the following primary parts, illustrated in the following tables. They include:
- Legacy PCI v3.0 Type 0/1 Configuration Space Header
- Legacy Extended Capability Items
-
- PCIe Capability Item
- Power Management Capability Item
- Message Signaled Interrupt (MSI) Capability Item
- MSI-X Capability Item (optional)
- PCIe Capabilities
-
- Advanced Error Reporting Extended Capability Structure (AER)
- Alternate Requester ID (ARI) (optional)
- Device Serial Number Extended Capability Structure (DSN) (optional)
- Single Root I/O Virtualization (SR-IOV) (optional)
- Virtual Channel Extended Capability Structure (VC) (optional)
- PCIe Extended Capabilities
-
- Device Serial Number Extended Capability Structure (optional)
- Virtual Channel Extended Capability Structure (optional)
- Advanced Error Reporting Extended Capability Structure (optional)
- Media Configuration Access Port (MCAP) Extended Capability Structure (optional)
The core implements up to four legacy extended capability items.
For more information about enabling this feature, see Customizing and Generating the Core.
The core can implement up to ten PCI Express Extended Capabilities.
The remaining PCI Express Extended Capability Space is available for users to
implement. The starting address of
the space available to users begins at 3DCh.
If you
choose to implement registers in this space, you can select the starting location of
this space, and this space must be implemented in the user application.
| Byte Offset | Register (Type 0: Endpoint) | Register Type 1: Root/DS Port) | ||||||
|---|---|---|---|---|---|---|---|---|
| 00h | Device ID | Vendor ID | same as Endpoint | |||||
| 04h | Status | Command | ||||||
| 08h | Class Code | Rev ID | ||||||
| 0Ch | BIST | Header | Lat Tim | CacheL | ||||
| 10h | BAR0 | |||||||
| 14h | BAR1 | |||||||
| 18h | BAR2 | SecLTim | SubBus# | SecBus# | PrimBus# | |||
| 1Ch | BAR3 | Secondary Status | I/O Lim | I/O Base | ||||
| 20h | BAR4 | Memory Limit | Memory Base | |||||
| 24h | BAR5 | PrefetchMemLimit | PrefetchMemBase | |||||
| 28h | Cardbus CIS Pointer | Prefetchable Base Upper 32 Bits | ||||||
| 2Ch | Subsystem ID | Subsystem Vendor ID | Prefetchable Limit Upper 32 Bits | |||||
| 30h | Expansion ROM BAR | I/O Limit Upper 16 | I/O Base Upper 16 | |||||
| 34h | Reserved | CapPtr | Reserved | CapPtr | ||||
| 38h | Reserved | Expansion ROM BAR | ||||||
| 3Ch | Max_Lat | Min_Gnt | IntrPin | IntrLine | Bridge Control | IntrPin | IntrLine | |
| Byte Offset (DW Offset) | Register (Endpoint) | Register (Root/DS Port) | ||||
|---|---|---|---|---|---|---|
| 40h (10h) | PM Capability | NxtCap | PM Cap ID | same as Endpoint | ||
| 44h (11h) | Data | BSE | PMCSR | |||
| 48h (12h) | MSI Control | NxtCap | MSI Cap ID | |||
| 4Ch (13h) | Message Address (Lower) | |||||
| 50h (14h) | Message Address (Upper) | |||||
| 54h (15h) | Reserved | Message Data | ||||
| 58h (16h) | Mask Bits | |||||
| 5Ch (17h) | Pending Bits | |||||
| 60h (18h) | MSIX Control | NxtCap | MSIX Cap ID | Reserved | ||
| 64h (19h) | Table Offset | Table BIR | Reserved | |||
| 68h (1Ah) | PBA Offset | PBA BIR | Reserved | |||
| 6Ch (1Bh) | Reserved | Reserved | ||||
| 70h (1Ch) | PCIE Capability | NxtCap | PCIE Cap ID | same as Endpoint | ||
| 74h (1Dh) | Device Capabilities | |||||
| 78h (1Eh) | Device Status | Device Control | ||||
| 7Ch (1Fh) | Link Capabilities | |||||
| 80h (20h) | Link Status | Link Control | ||||
| 84h (21h) | Reserved | Slot Capabilities | ||||
| 88h (22h) | Reserved | Slot Status | Slot Control | |||
| 8Ch (23h) | Reserved | Root Capabilities 1 | Root Control 1 | |||
| 90h (24h) | Reserved | Root Status 1 | ||||
| 94h (25h) | Device Capabilities 2 | same as Endpoint | ||||
| 98h (26h) | Device Status 2 | Device Control 2 | ||||
| 9Ch (27h) | Link Capabilities 2 | |||||
| A0h (28h) | Link Status 2 | Link Control 2 | ||||
| A4-FCh |
Unimplemented Configuration Space (Returns 00000000h) |
|||||
|
||||||
| PF0 | PF1-3 | VF | Start Address |
|---|---|---|---|
| Legacy PCI CSH | Legacy PCI CSH | Legacy PCI CSH | 0x00 |
| PM | PM | - | 0x40 |
| MSI | MSI | - | 0x48 |
| MSI-X | MSI-X | MSI-X | 0x60 |
| PCIE | PCIE | PCIE | 0x70 |
| Extend | Extend | 0xB0 |
| Byte Offset (DW Offset) | Register (Endpoint) | Register (Root Port) | ||||||
|---|---|---|---|---|---|---|---|---|
| 100h (40h) | Nxt Cap | Cap Ver | AER Ext Cap | same as Endpoint | ||||
| 104h (41h) | Uncorrectable Error Status Register | |||||||
| 108h (42h) | Uncorrectable Error Mask Register | |||||||
| 10Ch (43h) | Uncorrectable Error Severity Register | |||||||
| 110h (44h) | Correctable Error Status Register | |||||||
| 114h (45h) | Correctable Error Mask Register | |||||||
| 118h (46h) | Advanced Error Cap. & Control Register | |||||||
| 11Ch (47h) | Header Log Register 1 | |||||||
| 120h (48h) | Header Log Register 2 | |||||||
| 124h (49h) | Header Log Register 3 | |||||||
| 128h (4Ah) | Header Log Register 4 | |||||||
| 12Ch (4Bh) | Reserved | Root Error Command Register | ||||||
| 130h (4Ch) | Reserved | Root Error Status Register | ||||||
| 134h (4Dh) | Reserved | Error Source ID Register | ||||||
| 140h (50h) | Nxt Cap | Cap Ver | SR-IOV Ext Cap | Reserved | ||||
| 144h (51h) | Capability Register | |||||||
| 148h (52h) | SR-IOV Status | Control | ||||||
| 14Ch (53h) | Total VFs | Initial VFs | ||||||
| 150h (54h) | Func Dep Link | Number VFs | ||||||
| 154h (55h) | VF Stride | First VF Offset | ||||||
| 158h (56h) | VF Device ID | Reserved | ||||||
| 15Ch (57h) | Supported Page Sizes | |||||||
| 160h (58h) | System Page Size | |||||||
| 164h (59h) | VF Base Address Register 0 | |||||||
| 168h (5Ah) | VF Base Address Register 1 | |||||||
| 16Ch (5Bh) | VF Base Address Register 2 | |||||||
| 170h (5Ch) | VF Base Address Register 3 | |||||||
| 174h (5Dh) | VF Base Address Register 4 | |||||||
| 178h (5Eh) | VF Base Address Register 5 | |||||||
| 180h (60h) | Nxt Cap | Cap Ver | ARI Ext Cap | |||||
| 184h (61h) | Control | NxtFn | FnGrp | |||||
| 188h - 19Ch | Reserved | |||||||
| 1A0h (68h) | Nxt Cap | Cap Ver | DSN Ext Cap | |||||
| 1A4h (69h) | Device Serial Number (1st) | |||||||
| 1A8h (6Ah) | Device Serial Number (1st) | |||||||
| 1ACh - 1BCh | Reserved | |||||||
| 1C0h (70h) | Nxt Cap | Cap Ver | 2nd PCIE Ext Cap | same as Endpoint | ||||
| 1C4h (71h) | Lane Control | |||||||
| 1C8h (72h) | Reserved | Lane Error Status | ||||||
| 1CCh (73h) | Lane 1 Eq Ctrl Reg | Lane 0 Eq Ctrl Reg | ||||||
| 1D0h (74h) | Lane 3 Eq Ctrl Reg | Lane 2 Eq Ctrl Reg | ||||||
| 1D4h (75h) | Lane 5 Eq Ctrl Reg | Lane 4 Eq Ctrl Reg | ||||||
| 1D8h (76h) | Lane 7 Eq Ctrl Reg | Lane 6 Eq Ctrl Reg | ||||||
| 1DCh (77h) | Lane 9 Eq Ctrl Reg | Lane 8 Eq Ctrl Reg | ||||||
| 1E0h (78h) | Lane 11 Eq Ctrl Reg | Lane 10 Eq Ctrl Reg | ||||||
| 1E4h (79h) | Lane 13 Eq Ctrl Reg | Lane 12 Eq Ctrl Reg | ||||||
| 1E8h (7Ah) | Lane 15 Eq Ctrl Reg | Lane 14 Eq Ctrl Reg | ||||||
| 1ECh (7Bh) | Lane 1 Eq Ctrl 2 Reg | Lane 0 Eq Ctrl 2 Reg | ||||||
| 1F0h (7Ch) | Lane 3 Eq Ctrl 2 Reg | Lane 2 Eq Ctrl 2 Reg | ||||||
| 1F4h (7Dh) | Lane 5 Eq Ctrl 2 Reg | Lane 4 Eq Ctrl 2 Reg | ||||||
| 1F8h (7Eh) | Lane 7 Eq Ctrl 2 Reg | Lane 6 Eq Ctrl 2 Reg | ||||||
| 1FCh (7Fh) | Reserved | Reserved | ||||||
| 200h(80h) | Nxt Cap | Cap Ver | VC Ext Cap | |||||
| 204h(81h) | Port VC Capability Register 1 | |||||||
| 208h(82h) | Port VC Capability Register 2 | |||||||
| 20Ch(83h) | Port VC Status | |||||||
| 210h (84h) | VC Resource Capability Register 0 | |||||||
| 214h (85h) | VC Resource Control Register 0 | |||||||
| 218h (86h) | VC Resource Stat 0 | |||||||
| 21Ch (87h) | Reserved | |||||||
| 220h (88h) | Nxt Cap | Cap Ver | TPH Ext Cap | |||||
| 224h (89h) | TPH Requester Capability Register | |||||||
| 228h (8Ah) | TPH Requester Control Register | |||||||
| 22Ch (8Bh) - 32Ch | TPH ST Table | |||||||
| 330h (CCh) | Reserved | Nxt Cap | Cap Ver | Loopback VSEC | ||||
| 334h (CDh) | Loopback Header | |||||||
| 338h (CEh) | Loopback Control | |||||||
| 33Ch (CFh) | Loopback Status | |||||||
| 340h (D0h) | Error Count 1 | |||||||
| 344h (D1h) | Error Count 2 | |||||||
| 348h (D2h) | Error Count 3 | |||||||
| 34Ch (D3h) | Error Count 4 | |||||||
| 350h (D4h) | Nxt Cap | Cap Ver | MCAP VSEC | Reserved | ||||
| 354h (D5h) | MCAP Header | |||||||
| 358h (D6h) | JTAG ID | |||||||
| 35Ch (D7h) | Bitstream Version | |||||||
| 360h (D8h) | Status Register | |||||||
| 364h (D9h) | Control Register | |||||||
| 368h (DAh) | Data Register | |||||||
| 36Ch (DBh) | Register Read Data 0 | |||||||
| 370h (DCh) | Register Read Data 1 | |||||||
| 374h (DDh) | Register Read Data 2 | |||||||
| 378h (DEh) | Register Read Data 3 | |||||||
| 37Ch - FFCh | Reserved | |||||||
| PF0 | PF1-3 | VF | Start Address | PF0 Next Pointer |
|---|---|---|---|---|
| PCI Express Extended Configuration Space Enable | PCI Express Extended Configuration Space Enable | PCI Express Extended Configuration Space Enable | 0x0 | PCIE4: 0x480 |
| PCIE4C: 0xE80 |