The following table defines the Configurator example design file structure.
| File | Description |
|---|---|
| xilinx_pcie4_uscale_rp.v | Top-level wrapper file for Configurator example design |
| cgator_wrapper.v | Wrapper for Configurator and Root Port |
| cgator.v | Wrapper for Configurator sub-blocks |
| cgator_cpl_decoder.v | Completion decoder |
| cgator_pkt_generator.v | Configuration TLP generator |
| cgator_tx_mux.v | Transmit AXI4-Stream muxing logic |
| cgator_gen2_enabler.v | 5.0 Gbps directed speed change module |
| cgator_controller.v | Configurator transmit engine |
| cgator_cfg_rom.data | Configurator ROM file |
| pio_master.v | Wrapper for PIO Master |
| pio_master_controller.v | TX and RX Engine for PIO Master |
| pio_master_checker.v | Checks incoming User-Application Completion TLPs |
| pio_master_pkt_generator.v | Generates User-Application TLPs |
The hierarchy of the Configurator example design is:
xilinx_pcie_uscale_rp.v
-
cgator_wrapper-
pcie_uscale_core_top(in the source directory): This directory contains all the source files for the core in Root Port Configuration. -
cgator
- cgator_cpl_decoder
- cgator_pkt_generator
- cgator_tx_mux
- cgator_gen2_enabler
-
cgator_controller: This directory
contains
<cgator_cfg_rom.data>(specified by ROM_FILE).
-
-
pio_master-
pio_master_controller -
pio_master_checker -
pio_master_pkt_generator
-
Note:
cgator_cfg_rom.data is the default name of the ROM data file. You can
override this by changing the value of the ROM_FILE parameter.