The second difference is the design structure. In order to swap one user application from one version to the next, it must be completely enclosed within its own level of hierarchy. The interface of this instantiation cannot change; otherwise, the top-level static design needs to be recompiled. Everything other than the UltraScale+ Devices Integrated Block for PCIe core (in its own level of hierarchy below top) and any I/O logic (buffers, etc.) that are placed in bank 65 are in this level of hierarchy (and below). This means that all I/O logic for all other banks must be placed here and not inferred at the top level, so instantiation of I/O buffers is required.
This also means that any IP must be completely contained in the dynamic Update Region, as they are not permitted to straddle stage 1 (the PCIe region and bank 65, shown in pink in the image above) and stage 2 (the Reconfigurable Partition, yellow). The DFX design flow is based on the design hierarchy to ensure separation of static and dynamic domains, and modules cannot be in both domains at once.
Another requirement of the design structure is that all elements to be placed in the configuration frame must also be part of this top-level design (or another level of hierarchy separate from the PCIe IP and the user application). These elements include the BSCAN, ICAP, STARTUP and related components. See Vivado Design Suite User Guide: Dynamic Function eXchange (UG909) for the complete list. The elements must be hierarchically isolated because they are not permitted to be dynamically reconfigured. The implications of this mean that IP cores that require these elements, such as the Vivado Debug Hub and the Memory Interface Generator (MIG), which both use BSCAN, must take special precautions to be safely implemented. For details, see Debugging Tandem PCIe with Field Updates Designs.
All other considerations for Tandem Configuration are still applicable for Tandem PCIe with Field Updates.