Feature Overview - 1.3 English

The following figure illustrates the user interface of the core.

Figure 1. Block Diagram of Integrated Block User Interfaces

The interface is organized as four separate interfaces through which data can be transferred between the PCIe link and the user application:

• A PCIe Completer Request (CQ) interface through which requests arriving from the link are delivered to the user application.
• A PCIe Completer Completion (CC) interface through which the user application can send back responses to the completer requests. The user application can process all Non-Posted transactions as split transactions. That is, it can continue to accept new requests on the completer request interface while sending a completion for a request.
• A PCIe Requester Request (RQ) interface through which the user application can generate requests to remote PCIe devices attached to the link.
• A PCIe Requester Completion (RC) interface through which the user application receives completions from the link (in response to the user application requests as PCIe requester).

Each of the four interfaces is based on the AMBA® AXI4-Stream Protocol Specification. The width of these interfaces can be configured as 64, 128, 256, or 512 bits, and the user clock frequencies can be selected as 62.5, 125, or 250 MHz, depending on the number of lanes and data rate you choose. Only the Gen3 x16 interface has a data of 512 bits (64 bytes), and operates at a clock frequency of 250 MHz, providing a peak transfer rate of 16 GB/s in each direction, adequate to support a Gen3 x16 PCI Express® link.

The following table lists the valid combinations of interface width and user clock frequency for the different link widths and link speeds supported by the integrated block. All four AXI4-Stream interfaces are configured with the same width in all cases.