The GTH and GTY transceivers in the PCIe4 and PCIe4C integrated blocks solution support 1-lane, 2-lane, 4-lane, 8-lane, and 16-lane operation, running at 2.5 GT/s (Gen1), 5.0 GT/s (Gen2), and 8.0 GT/s (Gen3) line speeds. Additionally, the PCIe4C integrated block supports 1-lane, 2-lane, 4-lane and 8-lane operation running at 16.0 GT/s (Gen4) line speed. Endpoint and Root Port configurations are supported.
The customer user interface is compliant with the AMBA® AXI4-Stream interface. This interface supports separate Requester, Completion, and Message interfaces. It allows for flexible data alignment and parity checking. Flow control of data is supported in the receive and transmit directions. The transmit direction additionally supports discontinuation of in-progress transactions. Optional back-to-back transactions use straddling to provide greater link bandwidth.
- PCIE4 and PCIE4C blocks are compliant with PCI Express Base Specification, rev3.1 .
- PCI Express Endpoint, Legacy Endpoint or Root Port Modes
- Both PCIE4 and PCIE4C blocks: x1, x2, x4, x8, or x16 link widths with Gen1, Gen2, and Gen3 link speeds
- PCIE4C block: x1, x2, x4, and x8 link widths with Gen4 link speeds
-
AXI4 Streaming Interface to
customer logic
- Configurable 64-bit/128-bit/256-bit/512-bit datapath widths
- Four Independent Request/Completion Streams
- Parity protection on internal logic datapaths and data interfaces
- Advanced Error Reporting (AER) and End-to-End CRC (ECRC)
- One PCI Express virtual channel, eight traffic classes
- Supports multiple functions and Single-Root I/O Virtualization
- Up to 4 physical functions
- Up to 252 virtual functions
- Built-in lane reversal and receiver lane-to-lane de-skew
- 3 x 64-bit, or 6 x 32-bit Base Address Registers (BARs) that are fully
configurable
- Expansion ROM BAR supported
- Maximum Payload Size: 128, 256, 512, and 1024 bytes
- All Interrupt types are supported:
- INTx
- 32 multi-vector MSI capability
- MSI-X capability with up to 2048 vectors with optional, built-in MSI-X vector tables
- Built-in Initiator Read Request/Completion Tag Manager
- Up to 256 outstanding Initiator Read Request Transactions supported
- Dynamic Reconfiguration Port (DRP) port supported
- Features that enable high performance applications:
- AXI4 Streaming Transaction Layer Packets (TLP) Straddle on Requester Completion Interface
- Up to 256 RX Completion Header Credits and 32 kilobyte RX Completion Payload Space
- Relaxed Transaction Ordering in the Receive Datapath
- Address Translation Services (ATS) Messaging
- Atomic Operation Transactions Support
- TLP Processing Hints (TPH)
- Several ease of use and configurability features are
supported:
- BAR and ID based filtering of Received Transactions
- ASPM Optionality
- Configuration Extend Interface
- AXI4 Streaming Interfaces Address Align Mode
- Configuration over PCI Express media configuration access port (MCAP), and 100 ms power on to configuration (Support in the IP core is planned for a future release)
- Debug and Diagnostics Interface