- Designed to comply with the PCI Express Base Specification, rev3.1 .
- PCI Express® Endpoint, Legacy Endpoint, or Root Port Modes.
- x1, x2, x4, x8, or x16 link widths with Gen1, Gen2, and Gen3 link speeds for both PCIe4 and PCIe4C blocks.
- x1, x2, x4, and x8 link widths with Gen4 link speeds for the PCIe4C block.
- AXI4-Stream Interface to customer logic.
- Advanced Error Reporting (AER) and End-to-End CRC (ECRC).
- Block RAM used for Transaction buffering.
- One PCI Express virtual channel, and eight traffic classes.
- Up to 4 physical functions and 252 virtual functions.
- 3 x 64-bit, or 6 x 32-bit Base Address Registers (BARs) that are fully configurable.
For a full list of features, see Feature Summary.