GT DRP Ports - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2023-10-19
Version
1.3 English

The following table list the signals that are available when the GT Channel DRP parameter is enabled.

Table 1. GT DRP Ports
Name I/O Width Description
ext_ch_gt_drpaddr I Number Of Lanes x 10 GT Wizard DRP address
ext_ch_gt_drpen I Number Of Lanes x 1 GT Wizard DRP enable
ext_ch_gt_drpdi I Number Of Lanes x 16 GT Wizard DRP data in
ext_ch_gt_drpdo O Number Of Lanes x 16 GT Wizard DRP data out
ext_ch_gt_drprdy O Number Of Lanes x 1 GT Wizard DRP ready
ext_ch_gt_drpwe I Number Of Lanes x 1 GT Wizard DRP write/read