GT Locations - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
Document ID
PG213
Release Date
2023-10-19
Version
1.3 English
This appendix provides a list of GTs locations available for this IP core and lists some key recommendations that should be considered when selecting the GT location. The following sections include tables which identify which GT Banks are available for selection based on the PCIe block location as selected during IP customization.
  • AMD Artix™ AMD UltraScale+™ Devices Available GT Quads
  • AMD Kintex™ UltraScale+™ Devices Available GT Quads
  • AMD Virtex™ UltraScale+™ Devices Available GT Quads
  • AMD Zynq™ AMD UltraScale+™ Devices Available GT Quads
A GT Quad is comprised of four GT lanes. When selecting GT Quads for the PCIe IP, AMD recommends that you use the GT Quad most adjacent to the PCIe hard block. While this is not required, it will improve place, route, and timing for the design.
  • Link widths of x1, x2, and x4 require one bonded GT Quad and should not split lanes between two GT Quads.
  • A link width of x8 requires two adjacent GT Quads that are bonded and are in the same SLR.
  • A link width of x16 requires four adjacent GT Quads that are bonded and are in the same SLR.

PCIe lane 0 is placed in the topmost GT of the top-most GT Quad by default (as shown in AMD Vivado™ Integrated Design Environment (IDE) Device view). Subsequent lanes use the next available GTs moving vertically down the device as the lane number increments. This means that by default the highest PCIe lane number uses the bottom-most GT in the bottom-most GT Quad that is used for PCIe. During IP customization, you can select the desired GT Quad for PCIe lane 0 from the drop-down selections.

The PCIe reference clock (sys_clk_p/sys_clk_n) uses GTREFCLK0 in the PCIe lane 0 GT Quad for x1, x2, x4, and x8 configurations by default. For x16 configurations, the PCIe reference clock should use GTREFCLK0 on a GT Quad associated with lanes 4-7 or lanes 8-11. This allows the clock to be forwarded to all 16 PCIe lanes. You can modify the reference clock default location by adding pin location constraints to the design.

The following diagrams show the ideal GT Quad and reference clock selections for various PCIe link configurations relative to the PCIe block location for a representative device.

Figure 1. Most Adjacent GT Quad Location For x1, x2, x4 PCIe Link Width
Figure 2. Most Adjacent GT Quads For x8 PCIe Link Width
Figure 3. Most Adjacent GT Quads For x16 PCIe Link Width

Some PCIe locations have non-ideal GT Quad selections as result of their proximity to the edge of the device, SLR boundary, or other PCIe blocks. In these scenarios the most adjacent GTs may not be optimal for place and route, but will work as desired. The figure below shows one common example.

Figure 4. Alternative PCIe GT Location Selection

The sections below provide device lists with possible GT Quads selection support for each link width configuration. For example, when you select XCVU27P-FSGA2577 device, two combinations of GTY Quads for x8 link width are supported.

  • The first option is GTY_Quad_225 with GTY_Quad_224 when the selection is GTY_Quad_225 in the GUI.
  • The second option is GTY_Quad_226 with GTY_Quad_225 when the selection is GTY_Quad_226 in the GUI.