Settings in this page allow you to customize specific transceiver settings that are normally not accessible.
Figure 1. GT Settings Tab
- PLL Selection
- (Only available when Gen2 link speed is selected), allows for
either the QPLL1 or CPLL to be selected as the clock source. This feature is
useful when additional protocols are desired to be in the same GT Quad when
operating at Gen2 links speeds. Gen3 speeds require the QPLL1, and Gen1 speeds
always use the CPLL.Important: The rest of the settings should not be modified unless instructured to do so by AMD.
The following table shows the options and default for each line speed.
Table 1. PLL Type Link Speed PLL Type Comments 2.5_GT/s CPLL The default is CPLL, and not available for selection. 5.0_GT/s QPLL1, CPLL The default is QPLL1, and available for selection. 8.0_GT/s QPLL1 The default is QPLL1, and not available for selection. - Enable Auto RxEq
- When this parameter is set to True, it auto select the Receiver
Equalization (LPM or DFE) mode.
- True
- The default is DFE, but it will change LPM based on the channel characteristics.
- False
- The default is DFE and can be changed by setting the Form Factor Driven Insertion Loss Adjustment.
- Form Factor Driven Insertion Loss Adjustment
- Indicates the transmitter to receiver insertion loss at the
Nyquist frequency depending on the form factor selection. Three options are provided:
- Chip-to-Chip
- The value is 5 dB.
- Add-in Card
- The value is 15 dB and is the default option.
- Backplane
- The value is 20 dB.
These insertion loss values are applied to the GT Wizard subcore.
- Link Partner TX Preset
- It is not advisable to change the default value of 4. Preset value of 5 might work better on some systems. This parameter is available on GT Settings tab.
- GT DRP Clock Source
- This option is added to select the GT clock source external or internal. When External is selected, the DRP Clock is supplied from an external clock source of 300 MHz, and it will be divided into 100/125 MHz in the AMD top module. The default GT DRP clock source is Internal but is External when Enable In System IBERT is enabled in the Add. Debug Options page.