Hardware Operation Details - 1.3 English

The initial configuration of the device is no different than the normal Tandem Configuration. Initial configuration of the device consists of two stages, as two separate bitstreams (one loaded using flash, one loaded over PCIe) using the Tandem PCIe approach. After the stage 1 is loaded, only the PCIe IP is operational, with limited functionality as the rest of the design behind it does not yet exist. It is able to link train and be recognized by the Root Port in the system. After the stage 2 bitstream is loaded, the devices is in normal operational mode.

Subsequent dynamic updates follow the fundamental rules for UltraScale+ device Dynamic Function eXchange, but using the different verX stage 2 bitstreams as partial bitstreams. When loading over the link, logic decoupling is managed by the PCIe drivers automatically.

Using the bitstream names for a Tandem PCIe design and the supplied scripts, the sequence would look like this:

1. Power on the FPGA. ver1_tpcie_tandem1.mcs is sent from local flash.
   • At this point, the PCIe Endpoint is functional, and enumeration can occur.
   • The PCIe core is isolated from the rest of the unconfigured device.
2. Deliver ver1_tpcie_tandem2.bin over the PCIe link.
   • The complete device is now programmed, and the design switches automatically to full use mode by establishing communication between PCIe and the rest of the design.
   • Alternately, ver2_tpcie_update_region_partial.bin could also be sent over the PCIe link to complete the initial programming of the device.
3. Operate the FPGA for as long as you would like.
4. When a request to update is received, deliver the new user application by sending ver2_tpcie_update_region_partial.bin over the PCIe link.
   • The full device is once again operational, now with new functionality.
   • The switchover from isolation of the PCIe to full operation happens automatically.
5. Repeat step 4 to move on to a new version (or return to ver1).