Important Considerations - 1.3 English

These considerations are critical for safe and reliable operation of the target device.

• Always be sure that the stage 2 bitstreams are compatible with the current static design in the FPGA before loading them. PR_Verify is a fundamental part of the Dynamic Function eXchange solution and must be used for Tandem PCIe with Field Updates for the same reason. PR_Verify confirms that multiple design configurations (i.e., versions) are compatible with each other and therefore safe to overlay in hardware.
• The initial Tandem configuration of the device must be done with a bitstream set compiled as a version within a Tandem PCIe with Field Updates flow. If the initial bitstream load has been done with a standard Tandem bitstream set, it will not be compatible with later Field Update partial bitstreams. Contention could occur and device damage is possible.
• Tandem PCIe with Field Updates using Reconfigurable Stage Twos is for UltraScale+ devices only. Field Updates will never support 7 series devices, and the Reconfigurable Stage Twos enhancement will never support UltraScale devices. For this type of approach, a general Dynamic Function eXchange solution should be considered.
• General Tandem PCIe + DFX is also supported. This use case allows you to create smaller and/or more numerous Reconfigurable Partitions in a design that utilizes a Tandem initial boot. This flow should be considered more like a standard DFX flow that also has the PCIe IP in the static design. To enable, simply use the standard Tandem PCIe option when generating the PCIe IP, and then add it to a DFX design. This can be compiled in project or non-project mode, with the only unique requirement being that the Pblocks for the respective solutions cannot overlap.