Loading Stage 2 Through PCI Express - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2023-10-19
Version
1.3 English

An example kernel mode driver and user space application is provided with the IP. For information on retrieving the software and documentation, see AR 64761.

It is critical to remember that Tandem PCIe stages must remain linked. Stage 1 and stage 2 bitstreams are created from a single routed design image, and any changes to this design means that both stages must be updated. Stage 2 bitstreams for Tandem PCIe must only be delivered exactly one time to complete a full device configuration. If different/new stage 2 images or the ability to reload stage 2 is desired, you must use the Field Updates methodology. This solution adds DFX, meaning locked interface ports and multiple design runs ensure compatibility of multiple stage 2 bitstreams for a given fixed stage 1 bitstream.