Method 1 – Using the Existing PCI Express Example Design - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)

Document ID
PG213
Release Date
2023-10-19
Version
1.3 English
This is the simplest method in terms of what must be done with the PCI Express core, but might not be feasible for all users. If this approach meets your design structure needs, follow these steps.
  1. Create the example design.

    Generate the example design as described in Tandem PROM UltraScale+ Example Tool Flow and Tandem PCIe UltraScale+ Example Tool Flow.

  2. Insert the user application.

    Replace the PIO example design with the user design. It is recommended that the global and top-level elements, such as I/O and global clocking, be inserted in the top-level design.

  3. Uncomment and modify the SPI or BPI flash memory programming settings as required by your board design.
  4. Implement the design as normal.