- Create the example design.
Generate the example design as described in Tandem PROM UltraScale+ Example Tool Flow and Tandem PCIe UltraScale+ Example Tool Flow.
- Migrate the external GT wizard.
If the Include GT Wizard in example design option is set in the Shared Logic tab during core generation, then the GT Wizard IP is instantiated in the top level of the example design. This GT Wizard IP should be migrated to the user design to provide the necessary GT connections.
- Migrate the top-level constraint.
The example Xilinx design constraints (XDC) file contains timing constraints, location constraints, and Pblock constraints for the PCIe core. All of these constraints (other than the I/O location and I/O standard constraints) need to be migrated to the user design. Several of the constraints contain hierarchical references that require updating if the hierarchy of the design is different than the example design.
- Migrate the top-level Pblock constraint.
The following constraint is easy to miss so it is called out specifically in this step. The Pblock constraint should point to the top level of the PCIe core.
add_cells_to_pblock [get_pblocks main_pblock_boot] [get_cells -quiet [<path>]]Important: Do not make any changes to the physical constraints defined in the XDC file because the constraints are device dependent. - Add the Tandem PCIe IP to the Vivado
project.
Click Add Sources in the Flow Navigator. In the Add Source wizard, select Add Existing IP and then browse to the XCI file that was used to create the Tandem PCIe example design.
- Copy the appropriate SPI or BPI flash memory settings from the example design XDC file and paste them in your design XDC file.
- Implement the design as normal.
In cases where it is not possible to use Method 1 above, the following steps should be
followed to use the PCIe core and the desired Tandem flow (PROM or
PCIe) in a new project. The example project has many of the
required RTL and scripts that must be migrated into the user design.