In general, to achieve the best (smallest) first-stage bitstream size, you should place the PCIe reset package pin in bank 65 with the other configuration pins. If a new location for the reset pin is needed, you should consider the location for any I/Os that are intended to be configured in stage 1. I/Os that are physically placed a long distance from the core cause extra configuration frames to be included in the first stage. This is due to extra routing resources that are required to include these I/Os in the first stage.
Regardless of where the reset pin is located, bank 65 should still be kept in stage 1.
Even if configuration modes such as QSPI are used, the EMCCLK is
required for the fastest possible configuration, and that dual-mode pin is located in
bank 65.