PCIe DRP Ports - 1.3 English

UltraScale+ Devices Integrated Block for PCI Express Product Guide (PG213)
Document ID
PG213
Release Date
2023-10-19
Version
1.3 English

The following table lists the signals that are available when the PCIe DRP Ports option is selected.

Table 1. PCIe DRP Ports
Name I/O Width Description
drp_addr I 10 bits PCIe DRP address
drp_en I 1 bit PCIe DRP enable
drp_di I 16 bits PCIe DRP data in
drp_do O 16 bits PCIe DRP data out
drp_rdy O 1 bit PCIe DRP ready
drp_we I 1 bit PCIe DRP write/read