PIO Hardware - 1.3 English

For Address Align Mode, the PIO design implements an 8,192 byte target space in FPGA block RAM, behind the Endpoint for PCIe. This 32-bit target space is accessible through single Dword I/O Read, I/O Write, Memory Read 64, Memory Write 64, Memory Read 32, and Memory Write 32 TLPs.

The PIO design generates a completion with one Dword of payload in response to a valid Memory Read 32 TLP, Memory Read 64 TLP, or I/O Read TLP request presented to it by the core. In addition, the PIO design returns a completion without data with successful status for I/O Write TLP request. For Dword Align Mode, the PIO design implements 2048-byte target space in FPGA block RAM. This target space, and data width varies based on the AXI4-Stream interface and is equal to the width of the AXI4-Stream interface. This target space is accessible through Memory Write 32 and Memory Read 32 TLPs.

The PIO generates a completion with the payload size in response to a valid Memory Read 32 TLP request from the core.

The PIO design can initiate the following:

• a Memory Read transaction when the received write address is 11'hEA8 and the write data is 32'hAAAA_BBBB, and targeting the BAR0.
• a Legacy Interrupt when the received write address is 11'hEEC and the write data is 32'hCCCC_DDDD, and targeting the BAR0.
• an MSI when the received write address is 11'hEEC and the write data is 32'hEEEE_FFFF, and targeting the BAR0.
• an MSIX when the received write address is 11'hEEC and the write data is 32'hDEAD_BEEF, and targeting the BAR0.

The PIO design processes a Memory or I/O Write TLP with one Dword payload in case of address align mode and multi-Dword in case of Dword Align Mode by updating the payload into the target address in the FPGA block RAM space.