The user application must transfer each request to be transmitted on the link to the requester request interface of the core as an independent AXI4-Stream packet. Each packet must start with a descriptor, and can have payload data following the descriptor. The descriptor is always 16 bytes long, and must be sent in the first 16 bytes of the request packet. The descriptor is transferred during the first two beats on a 64-bit interface, and in the first beat on a 128-bit or 256-bit interface. The formats of the descriptor for different request types are illustrated in the following figures.
The format of the following figure applies when the request TLP being transferred is a memory read/write request, an I/O read/write request, or an Atomic Operation request.
The format of the following figure is used for Vendor-Defined Messages (Type 0 or Type 1) only.
The format of the following figure is used for all ATS messages (Invalid Request, Invalid Completion, Page Request, PRG Response).
For all other messages, the descriptor takes the format of the following figure.
Bit Index | Field Name | Description |
---|---|---|
1:0 | Address Type |
This field is defined for memory transactions and Atomic Operations only. The core copies this field into the AT of the TL header of the request TLP.
|
63:2 | Address |
This field applies to memory, I/O and Atomic Op requests.
This is the address of the first Dword referenced by the request.
The user logic must also set the First_BE and Last_BE bits in
When the transaction specifies a 32-bit address, bits [63:32] of this field must be set to 0. |
74:64 | Dword Count |
These 11 bits indicate the size of the block (in Dwords) to be read or written (for messages, size of the message payload). Its range is 0 – 256 Dwords. For I/O accesses, the Dword count is always 1. For a zero length memory read/write request, the Dword count
must be 1, with the The core does not check the setting of this field against the actual length of the payload supplied (for requests with payload), nor against the maximum payload size or read request size settings of the core. |
78:75 | Request Type | Identifies the transaction type. The transaction types and their encodings are listed in the following table. |
79 | Poisoned Request | This bit can be used by the user logic to poison the request TLP being sent. This bit must be set to 0 for all requests, except when the user logic has detected an error in the block of data following the descriptor and wants to communicate this information using the Data Poisoning feature of PCI Express. |
87:80 |
Requester Function/ Device Number |
Device and/or Function number of the Requester Function. Endpoint mode:
Upstream Port for Switch use case (Endpoint mode is selected within the IP):
Root Port mode (Downstream Port):
|
95:88 | Requester Bus Number |
Bus number associated with the Requester Function. Endpoint mode:
Upstream Port for Switch use case (Endpoint mode is selected within the IP):
Root Port mode (Downstream Port):
|
103:96 | Tag |
PCIe Tag associated with the request. For Posted
transactions, the core always uses the value from this field as the tag
for the request. For Non-Posted transactions, the core uses the value from this field if the Enable Client Tag is set during core configuration in the Vivado IDE (that is, when tag management is performed by the user logic). If this attribute is not set, tag management logic in the core is responsible for generating the tag to be used, and the value in the tag field of the descriptor is not used. |
119:104 | Completer ID | This field is applicable only to Configuration requests and messages routed by ID. For these requests, this field specifies the PCI Completer ID associated with the request (these 16 bits are divided into an 8-bit bus number, 5-bit device number, and 3-bit function number in the legacy interpretation mode. In the ARI mode, these 16 bits are treated as an 8-bit bus number + 8-bit Function number.). |
120 | Requester ID Enable / T8 |
Endpoint mode:
Upstream Port for Switch use case (Endpoint mode is selected within the IP):
Root Port mode:
|
123:121 | Transaction Class (TC) | PCIe Transaction Class (TC) associated with the request. |
126:124 | Attributes |
These bits provide the setting of the Attribute bits associated with the request. Bit 124 is the No Snoop bit, and bit 125 is the Relaxed Ordering bit. Bit 126 is the ID-Based Ordering bit, and can be set only for memory requests and messages. The core forces the attribute bits to 0 in the request sent on the link if the corresponding attribute is not enabled in the Function’s PCI Express Device Control Register. |
111:104 | Message Code |
This field is defined for all messages. It contains the 8-bit Message Code to be set in the TL header. Appendix F of the PCI Express 3.0 Specifications (available at http://www.pcisig.com/specifications) provides a complete list of the supported Message Codes. |
114:112 | Message Routing | This field is defined for all messages. The core copies these bits into the 3-bit Routing field r[2:0] of the TL header of the Request TLP. |
15:0 | Destination ID | This field applies to Vendor-Defined Messages only. When
the message is routed by ID (that is, when the Message Routing field is
010 binary), this field must be set to the
Destination ID of the message. |
63:32 | Vendor-Defined Header | This field applies to Vendor-Defined Messages only. It is copied into Dword 3 of the TL header. |
63:0 | ATS Header | This field is applicable to ATS messages only. It contains the bytes that the core copies into Dwords 2 and 3 of the TL header. |