Resets - 1.3 English

The core resets the system using sys_reset, an asynchronous, active-Low reset signal asserted during the PCI Express® Fundamental Reset. Asserting this signal causes a hard reset of the entire core, including the transceivers. Reset must be held asserted until the reference clock is stable as defined in the PCI Express Base Specification. After the reset is released, the core attempts to link train and resume normal operation. In a typical Endpoint application, for example an add-in card, a sideband reset signal is normally present and should be connected to sys_reset. For Endpoint applications that do not have a sideband system reset signal, the initial hardware reset should be generated locally.

Four reset events can occur in PCI Express:

Cold Reset

A Fundamental Reset that occurs at the application of power. The sys_reset signal is asserted to cause the cold reset of the core.

Warm Reset

A Fundamental Reset triggered by hardware without the removal and reapplication of power. The sys_reset signal is asserted to cause the warm reset to the core.

Hot Reset

In-band propagation of a reset across the PCI Express Link through the protocol, resetting the entire Endpoint device. In this case, sys_reset is not used. In the case of Hot Reset, the cfg_hot_reset_out signal is asserted to indicate the source of the reset.

Function-Level Reset

In-band propagation of a reset across the PCI Express Link through the protocol, resetting only a specific function. In this case, the core asserts the bit of either cfg_flr_in_process and/or cfg_vf_flr_in_process that corresponds to the function being reset. Logic associated with the function being reset must assert the corresponding bit of cfg_flr_done or cfg_vf_flr_done to indicate it has completed the reset process.

After an FLR has been initiated by writing a 1b to the Initiate Function Level Reset bit, the function must complete the FLR and any function-specific initialization within 100 ms.

The User Application interface of the core has an output signal, user_reset. This signal is deasserted synchronously with respect to user_clk. The user_reset signal is asserted as a result of any of these conditions:

Fundamental Reset

Occurs (cold or warm) due to assertion of sys_reset.

PLL within the Core Wrapper

Loses lock, indicating an issue with the stability of the clock input.

Loss of Transceiver PLL Lock

Any transceiver loses lock, indicating an issue with the PCI Express Link.

The user_reset signal is deasserted synchronously with user_clk after all of the listed conditions are resolved, allowing the core to attempt to train and resume normal operation.