Revision History - 1.3 English

SRIOV BARs Tab

Required Constraints

Verified and updated supported devices.

Added PCIE4C integrated block support details.

Added details about PCI Express Base Spec 4.0 compliance limitations.

Added Gen4 link speed to the Minimum Device Requirements for PCIE4C.

Added PCIEC and PCIE4 block locations to the Available Integrated Blocks for PCI Express - Virtex UltraScale+ table.

Added pcie_rq_tag0[7:0] and pcie_rq_tag1[7:0], which replace pcie_rq_tag.

Updated the cfg_ext_read_received description details.

In the “Configuration Received Message Interface” section, removed ATS message types from the Message Type Encoding on Receive Message Interface table, and the Message Parameters on Receive Message Interface table.

Added PCIE4 and PCIE4C block locations for supported Virtex UltaScale+

devices with high bandwidth memory (HBM).

Added devices to Available Integrated Blocks for PCI Express - Virtex UltraScale+ table.

Updated error_out to cfg_local_error_out in Configuration Status Interface

Port Descriptions table.

Updated the Tandem PROM/PCIe Supported Configurations table, and the Tandem PCIe with Field Updates section.

Added more detail to Clocking section.

Added important note to Lane Reversal section.

Added devices and packages to Virtex Ultrascale+ Devices Available GT Quads table, and Zynq UltraScale+ Devices Available GT Quads table.

Added Minimum Device Requirements for PCIE4C information.

Updated device support in the Tandem PROM/PCIe Supported Configurations table in the Designing with the Core chapter.

Added Integrated Debug Options section to Debugging appendix.

Removed Supported Devices table.

Updated description for Target Function field in the Completer Request Descriptor Fields table.

Updated description for Lower Address field in the Requester Completion Descriptor Fields table.

Added details about user_clk signal to Clock and Reset Interface section.

Added note regarding configuration bank 65 in the Tandem Configuration section.

Updated the Legacy Interrupt Signaling figure and description.

In Appendix A, “Upgrading”, added enable_auto_rxeq new parameter.

In Appendix B, “GT Locations”, all new content.

Updated “Available Integrated Blocks for PCI Express - Virtex UltraScale+” table.

Updated Sideband Signal Descriptions in m_axis_cq_tuser name/description for Bit Index 87:85.

Added cfg_err_cor_out, cfg_err_nonfatal_out, cfg_err_fatal_out, and cfg_ds_port_number.

Updated the description for sys_clk_gt.

Updated the Tandem Configuration section.

Updated the Clocking Architecture figure.

Major updates to description for Completer Completion Descriptor Fields (Bit Indexes 7972, 87:80, and 88), and Requester Request Descriptor Fields (Bit Indexes 87:80, 95:88, and 120).

Updated note in Handling of Completion Errors section.

Updated the following Vivado IP catalog option:

• Extended Tag Field (in the Capabilities tab).
• PF0 ID Initial Values > Device ID value (in Identity Setting (PF0 IDs and PF1 IDs) tab).
• MSIx Table Settings > Table Size (in MSI-X Capabilities tab).
• General SRIOV Config (in SRIOV Config tab)

Added new GT DRP Clock Source (in GT Settings tab), and GT COMMON Option (in Shared Logic tab)

In Appendix A, “Upgrading”, added new port and parameter details.

In Appendix B, “GT Location”, updated the tables: Virtex UltraScale+ Devices GT Locations, Zynq UltraScale+ Devices GT Locations, Kintex UltraScale+ Devices Available GT Quads, and Zynq Ultrascale+ Devices Available GT Quads

In Appendix C, “Debugging”, updated documented width for gt_dmonitorout port.

In Appendix D, “Using Xilinx Virtual Cable to Debug”:

• Added XVC Status Register
• Updated the Debug Bridge for XVC-PCIe-VSEC Register Map, and Debug Bridge for AXI-XVC Register Map tables.

Updated the Available Integrated Blocks for PCI Express - Zynq UltraScale+ table.

Updated port description for cfg_interrupt_msi_function_number.

Updated the TUSER signal in all AXI4-Stream Interface diagrams.

Updated the TUSER signal definition for the 512-bit AXI Interface including Straddle operation.

Minor updates to the Tandem Configuration section.

Updated pcie_cq_np_req to pcie_cq_np_req[0].

Added missing AXISTEN_IF_ENABLE_MSG_ROUTE Attribute Bit Descriptions table.

Updated the Zynq UltraScale+ Device GT Locations table.

Clarified the XCV driver and software example location in the Using Xilinx

Virtual Cable to Debug appendix.

Added the new Using Xilinx Virtual Cable to Debug appendix.

Updated the Tandem Configuration section.

Updated new Ports and Parameters information in the Upgrading appendix.

Updated the SRIOV BAR Size Ranges for Device Configuration table.

Added the PLL Selection and Link Partner TX Preset options in the GT Settings tab.

Clarified that the Enable In System IBERT, and Enable JTAG Debugger options should be used only for hardware debugging. Simulations are not supported for the cores generated using these options.

Moved the performance and resource utilization data to the web.

Updated the Minimum Device Requirements table.

Added tandem configuration support.

Added IBERT ports, GT DRP ports and PCIe ports used for transceiver debug, and the Vivado Design Suite core customization options that support them.

Added to Port Changes table in the Migrating and Upgrading appendix.

Updated the GT Locations table, and the Available Integrated Blocks for PCI Express table for Virtex UltraScale+ devices.

Completer Model option added for Root Port Model test bench.

MXI-X Interrupt Internal (built-in) support added.

GT Setting for insertion loss adjustment added.

QPLL1 support added in Gen2 (5Gb/s) mode.